> Half of this driver is a DM-based timer driver, and half is RISC-V-specific
> IPI code. Move the timer portions in with the other timer drivers. The
> KConfig is not moved, since it also enables IPIs. It could also be split
> into two configs, but no boards use the timer but not the IPI atm, so I
> haven't split it.
>
> Signed-off-by: Sean Anderson <sean...@gmail.com>
> ---
>
> MAINTAINERS | 1 +
> arch/riscv/lib/sifive_clint.c | 43 ++------------------------
> drivers/timer/Makefile | 1 +
> drivers/timer/sifive_clint_timer.c | 49 ++++++++++++++++++++++++++++++
> 4 files changed, 53 insertions(+), 41 deletions(-)
> create mode 100644 drivers/timer/sifive_clint_timer.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 32a2cdb52b..73d1c20a26 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -928,6 +928,7 @@ T: git
> https://gitlab.denx.de/u-boot/custodians/u-boot-riscv.git
> F: arch/riscv/
> F: cmd/riscv/
> F: drivers/timer/andes_plmt_timer.c
> +F: drivers/timer/sifive_clint_timer.c
> F: tools/prelink-riscv.c
>
> RISC-V KENDRYTE
> diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c
> index c9704c596f..c8079dc510 100644
> --- a/arch/riscv/lib/sifive_clint.c
> +++ b/arch/riscv/lib/sifive_clint.c
> @@ -1,5 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
> + * Copyright (C) 2020, Sean Anderson <sean...@gmail.com>
> * Copyright (C) 2018, Bin Meng <bmeng...@gmail.com>
> *
> * U-Boot syscon driver for SiFive's Core Local Interruptor (CLINT).
> @@ -8,19 +9,13 @@
> */
>
> #include <common.h>
> -#include <clk.h>
> #include <dm.h>
> -#include <timer.h>
> #include <asm/io.h>
> -#include <asm/syscon.h>
> +#include <asm/smp.h>
> #include <linux/err.h>
>
> /* MSIP registers */
> #define MSIP_REG(base, hart) ((ulong)(base) + (hart) * 4)
> -/* mtime compare register */
> -#define MTIMECMP_REG(base, hart) ((ulong)(base) + 0x4000 + (hart) * 8)
> -/* mtime register */
> -#define MTIME_REG(base) ((ulong)(base) + 0xbff8)
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -61,37 +56,3 @@ int riscv_get_ipi(int hart, int *pending)
>
> return 0;
> }
> -
> -static int sifive_clint_get_count(struct udevice *dev, u64 *count)
> -{
> - *count = readq((void __iomem *)MTIME_REG(dev->priv));
> -
> - return 0;
> -}
> -
> -static const struct timer_ops sifive_clint_ops = {
> - .get_count = sifive_clint_get_count,
> -};
> -
> -static int sifive_clint_probe(struct udevice *dev)
> -{
> - dev->priv = dev_read_addr_ptr(dev);
> - if (!dev->priv)
> - return -EINVAL;
> -
> - return timer_timebase_fallback(dev);
> -}
> -
> -static const struct udevice_id sifive_clint_ids[] = {
> - { .compatible = "riscv,clint0" },
> - { }
> -};
> -
> -U_BOOT_DRIVER(sifive_clint) = {
> - .name = "sifive_clint",
> - .id = UCLASS_TIMER,
> - .of_match = sifive_clint_ids,
> - .probe = sifive_clint_probe,
> - .ops = &sifive_clint_ops,
> - .flags = DM_FLAG_PRE_RELOC,
> -};
> diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
> index eda311f0f5..410ada87b7 100644
> --- a/drivers/timer/Makefile
> +++ b/drivers/timer/Makefile
> @@ -19,6 +19,7 @@ obj-$(CONFIG_RENESAS_OSTM_TIMER) += ostm_timer.o
> obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o
> obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
> obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o
> +obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint_timer.o
no _TIMER suffix ?
> obj-$(CONFIG_STI_TIMER) += sti-timer.o
> obj-$(CONFIG_STM32_TIMER) += stm32_timer.o
> obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o
> diff --git a/drivers/timer/sifive_clint_timer.c
> b/drivers/timer/sifive_clint_timer.c
> new file mode 100644
> index 0000000000..04e85c2564
> --- /dev/null
> +++ b/drivers/timer/sifive_clint_timer.c
> @@ -0,0 +1,49 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2020, Sean Anderson <sean...@gmail.com>
> + * Copyright (C) 2018, Bin Meng <bmeng...@gmail.com>
> + */
> +
> +#include <common.h>
> +#include <clk.h>
> +#include <dm.h>
> +#include <timer.h>
> +#include <asm/io.h>
> +#include <linux/err.h>
> +
> +/* mtime register */
> +#define MTIME_REG(base) ((ulong)(base) + 0xbff8)
> +
> +static int sifive_clint_get_count(struct udevice *dev, u64 *count)
> +{
> + *count = readq((void __iomem *)MTIME_REG(dev->priv));
> +
> + return 0;
> +}
> +
> +static const struct timer_ops sifive_clint_ops = {
> + .get_count = sifive_clint_get_count,
> +};
> +
> +static int sifive_clint_probe(struct udevice *dev)
> +{
> + dev->priv = dev_read_addr_ptr(dev);
> + if (!dev->priv)
> + return -EINVAL;
> +
> + return timer_timebase_fallback(dev);
> +}
> +
> +static const struct udevice_id sifive_clint_ids[] = {
> + { .compatible = "riscv,clint0" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(sifive_clint) = {
> + .name = "sifive_clint",
> + .id = UCLASS_TIMER,
> + .of_match = sifive_clint_ids,
> + .probe = sifive_clint_probe,
> + .ops = &sifive_clint_ops,
> + .flags = DM_FLAG_PRE_RELOC,
> +};
> --
> 2.28.0
LGTM.
Other than that,
Reviewed-by: Rick Chen <r...@andestech.com>
