Re: [U-Boot] [PATCH v4 3/7] usb: host: xhci-omap: fix double weak board_usb_init functions

On 23/02/17 15:39, Uri Mashiach wrote: > A weak version of the function board_usb_init is implemented in: > common/usb.c > drivers/usb/host/xhci-omap.c > > To fix the double implementations: > * Convert the board_usb_init function in drivers/usb/host/xhci-omap.c > normal (not weak). > * The fu

Re: [U-Boot] [linux-sunxi] Re: [PATCH 01/12] sunxi: Add initial support for R40

01.03.2017, 22:57, "Maxime Ripard" : > 1;4601;0c > On Wed, Mar 01, 2017 at 08:10:55PM +0800, Chen-Yu Tsai wrote: >>  On Wed, Mar 1, 2017 at 6:55 PM, Maxime Ripard >>   wrote: >>  > Hi Chen-Yu >>  > >>  > On Wed, Mar 01, 2017 at 03:04:36PM +0800, Chen-Yu Tsai wrote: >>  >> The R40 is the successor

Re: [U-Boot] i.MX6QP sd boot issue

Hi Fabio, On Wed, Mar 1, 2017 at 7:46 PM, Fabio Estevam wrote: > Hi Jagan, > > On Wed, Mar 1, 2017 at 9:55 AM, Jagan Teki wrote: >> + ML >> >> On Wed, Mar 1, 2017 at 6:23 PM, Jagan Teki wrote: >>> Hi Peng and All, >>> >>> I'm trying to boot from SD, on imx6qplus sabre board. >>> >>> - SW6: D1-D

Re: [U-Boot] [PATCH] arm: dra7xx: Update bootloader partition size

On Tue, Feb 21, 2017 at 09:51:31PM +0200, Sam Protsenko wrote: > The current size of U-Boot is already ~840 KiB. > > This patch is to increase bootloader partition size up to 1 MiB > and thereby fix flashing error. > > Also fix U-Boot environment address on eMMC ("reserved" partition), as > it's

Re: [U-Boot] Please pull u-boot-video/master

On Mon, Feb 27, 2017 at 04:22:54PM +0100, Anatolij Gustschin wrote: > Hi Tom, > > please pull two bug fixes for -rc3. Thanks! > > The following changes since commit a0f3e3df4adc451bf56159c0672e570f9c934ee8: > > travis-ci: Temporarily disable using a newer device tree compiler > (2017-02-26 1

Re: [U-Boot] [PATCH] arm: OMAP2+: nandecc: propagate error to command return status

On Sun, Feb 19, 2017 at 12:29:24AM +0100, Ladislav Michl wrote: Please explain the changes a little bit here, thanks! > Signed-off-by: Ladislav Michl -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de h

Re: [U-Boot] [U-Boot, 1/3] drivers/net/Kconfig: Correct use of apostrophe

On Mon, Feb 20, 2017 at 09:38:03AM -0500, Tom Rini wrote: > Signed-off-by: Tom Rini Applied prior to v2017.03-rc3 to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://list

Re: [U-Boot] [PULL] Please pull u-boot-imx

On Mon, Feb 27, 2017 at 06:08:59PM +0100, Stefano Babic wrote: > Hi Tom, > > please pull from u-boot-imx, thanks ! > > > The following changes since commit 66c246cce7c66019a93ff7105157c3e2126dd277: > > ARM: DRA7xx: Fix memory allocation overflow (2017-02-17 17:24:35 -0500) > > are available

Re: [U-Boot] [PATCH v3 00/10] stm32f7: add clock and pin control drivers

On Mon, Feb 27, 2017 at 05:33:58PM +, Vikas MANOCHA wrote: > Hi Tom, > > If it is ok, please apply this patchset. I'll pick it up early in the next release, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-

Re: [U-Boot] arm: mach-omap2: Flush cache after FIT post-processing image

On Wed, Feb 22, 2017 at 05:46:39PM -0600, Andrew F. Davis wrote: > After we authenticate/decrypt an image we need to flush the caches > as they may still contain bits of the encrypted image. This will > cause failures if we attempt to jump to this image. > > Reported-by: Yogesh Siraswar > Signed-

Re: [U-Boot] [PATCH 14/17] sunxi: Pine64: defconfig: enable SPL FIT support

Hi Andre, On Wed, Mar 01, 2017 at 02:25:26AM +, Andre Przywara wrote: > The Pine64 (and all other 64-bit Allwinner boards) need to load an > ARM Trusted Firmware image beside the actual U-Boot proper. > This can now be easily achieved by using the just extended SPL FIT > loading support, so en

Re: [U-Boot] [PATCH] armv5te: make 'ret lr' produce iinterworking 'bx lr'

On Mon, Feb 27, 2017 at 08:19:07PM +0100, Albert ARIBAUD wrote: > Current ARM assembler helper for the 'return to caller' pseudo-instruction > turns 'ret lr' into 'mov pc, lr' for ARMv5TE. This causes the core to remain > in its current ARM state even when the routine doing the 'ret' was called > f

Re: [U-Boot] [PATCH v5 16/16] sunxi: Add support for the CHIP Pro

On Mon, Feb 27, 2017 at 06:22:15PM +0100, Maxime Ripard wrote: > The CHIP Pro is a SoM that features the GR8 SIP, an AXP209, a BT/WiFi chip > and a 512MiB SLC NAND. > > This it's an SLC NAND, it doesn't suffer the same drawbacks than found on > the MLC NANDs, and we can enable it right away. > >

Re: [U-Boot] [PATCH v1] tools: Remove CONFIG_SYS_TEXT_BASE in Makefile

On Tue, Feb 28, 2017 at 07:29:11PM +0100, Patrick Delaunay wrote: > This define is not used in tools sources and can be removed > to avoid unnecessary link between tools and defconfig > > Signed-off-by: Patrick Delaunay Reviewed-by: Tom Rini -- Tom signature.asc Description: Digital signat

Re: [U-Boot] [linux-sunxi] Re: [PATCH 14/17] sunxi: Pine64: defconfig: enable SPL FIT support

2017年3月1日 23:51于 Maxime Ripard 写道： > > Hi Andre, > > On Wed, Mar 01, 2017 at 02:25:26AM +, Andre Przywara wrote: > > The Pine64 (and all other 64-bit Allwinner boards) need to load an > > ARM Trusted Firmware image beside the actual U-Boot proper. > > This can now be easily achieved by usi

Re: [U-Boot] [linux-sunxi] [PATCH 6/8] power: axp209: Add support for voltage rate control on LDO3

On Thu, Mar 2, 2017 at 12:02 AM, Olliver Schinagl wrote: > Hey Marcus, > > On 01-03-17 16:10, Marcus Weseloh wrote: >> >> Hi Oliver, >> >> 2017-03-01 13:52 GMT+01:00 Olliver Schinagl > >: >> >> +#define AXP209_VRC_LDO3_EN BIT(3) >> +#define AXP209_VRC

[U-Boot] [PATCH v2 0/8] spi: cadence: Fix read/write on socfpga

This patch series addresses two problems with reads/writes not working with the Cadence QSPI device on the socfpga arch. The first issue is reads/writes to the Cadence QSPI device do not work correctly with caching enabled on the socfpga. This problem was introduced with previous commits that use

[U-Boot] [PATCH v2 1/8] Revert "spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible"

This reverts commit 57897c13de03ac0136d64641a3eab526c6810387. The Cadence QSPI device does not work with caching (introduced with the bounce buffer in this commit) on the Altera SoC platform. Signed-off-by: Jason A. Rush --- Changed in v2: None drivers/spi/cadence_qspi_apb.c | 26 ++-

[U-Boot] [PATCH v2 2/8] Revert "spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible"

This reverts commit b63b46313ed29e9b0c36b3d6b9407f6eade40c8f. The Cadence QSPI device does not work with caching (introduced with the bounce buffer in this commit) on the Altera SoC platform. Signed-off-by: Jason A. Rush --- Changed in v2: None drivers/spi/cadence_qspi_apb.c | 22 ++---

[U-Boot] [PATCH v2 3/8] spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible

From: Vignesh R According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit data interface writes until the last word of an indirect transfer otherwise indirect writes is known to fails sometimes. So, make sure that

[U-Boot] [PATCH v2 4/8] spi: cadence_qspi: Cleanup register loading/accesses

Load the regbase/ahbbase 'reg' DT properties using the standard dev_get_addr_index function, and add __iomem to all register variables declarations. Signed-off-by: Jason A. Rush --- Changed in v2: None drivers/spi/cadence_qspi.c | 25 ++--- drivers/spi/cadence_qspi.h

[U-Boot] [PATCH v2 5/8] spi: cadence_spi: Add cdns, trigger-address DT property

The socfpga arch uses a different value for the indaddrtrig reg than the ahbbase address. Adopting the trigger-address DT bindings from the Linux kernel allows the indaddrtrig reg to be set correctly on the socfpga arch. Tested on Terasic SoCKit dev board (Altera Cyclone V) Signed-off-by: Jason A

[U-Boot] [PATCH v2 6/8] dts: socfpga: Add trigger-address property to QSPI device

Add the 'cdns,trigger-address' property to the cadence QSPI device node for Altera SoC devices. Signed-off-by: Jason A. Rush --- Changed in v2: - renamed trigger-base to trigger-address arch/arm/dts/socfpga.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/socfpga.dtsi b/ar

[U-Boot] [PATCH v2 7/8] dts: k2g: Add trigger-address property to QSPI device

Add the 'cdns,trigger-address' property to the cadence QSPI device node for Texas Instruments K2G SoC devices. Signed-off-by: Jason A. Rush --- Changed in v2: - renamed trigger-base to trigger-address arch/arm/dts/keystone-k2g.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/d

[U-Boot] [PATCH v2 8/8] dts: stv0991: Add trigger-address property to QSPI device

Add the 'cdns,trigger-address' property to the cadence QSPI device node for the ST STV0991 application board. Signed-off-by: Jason A. Rush --- Changed in v2: - renamed trigger-base to trigger-address arch/arm/dts/stv0991.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/stv0

Re: [U-Boot] [linux-sunxi] [PATCH 05/12] sunxi: Set PLL lock enable bits for R40

Hi! Dne sreda, 01. marec 2017 ob 08:04:40 CET je Chen-Yu Tsai napisal(a): > According to the BSP released by Banana Pi, the R40 (sun8iw11p1) has > an extra "PLL lock control" register in the CCU, which controls whether > the individual PLL lock status bits in each PLL's control register work > or

Re: [U-Boot] [PATCH] arm: dra7xx: Update bootloader partition size

On Wed, Mar 1, 2017 at 5:29 PM, Tom Rini wrote: > On Tue, Feb 21, 2017 at 09:51:31PM +0200, Sam Protsenko wrote: > >> The current size of U-Boot is already ~840 KiB. >> >> This patch is to increase bootloader partition size up to 1 MiB >> and thereby fix flashing error. >> >> Also fix U-Boot envir

[U-Boot] [PATCH v3 01/11] armv8: Add global variable resv_ram

Use gd->arch.resv_ram to track reserved memory allocation. Signed-off-by: York Sun --- Changes in v3: None Changes in v2: None arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 ++ arch/arm/include/asm/global_data.h| 3 +++ cmd/bdinfo.c | 4 3 files ch

[U-Boot] [PATCH v3 09/11] armv8: ls2080a: Drop early MMU for SPL build

Early MMU improves performance especially on emulators. However, the early MMU is left enabled after the first stage of SPL boot. Instead of flushing D-cache and dealing with re-enabling MMU for the second stage U-Boot, disabling it for SPL build simplifies the process. The performance penalty is u

[U-Boot] [PATCH v3 04/11] efi: Add a hook to allow adding memory mapping

Instead of adding all memory banks, add a hook so individual SoC/board can has its own implementation. Signed-off-by: York Sun CC: Alexander Graf Reviewed-by: Alexander Graf --- Changes in v3: None Changes in v2: Add change to efi mapping lib/efi_loader/efi_memory.c | 14 ++ 1

[U-Boot] [PATCH v3 02/11] armv8: ls2080a: Move CONFIG_FSL_MC_ENET to Kconfig

Use Kconfig option instead of config macro in header file. Clean up existing usage. Signed-off-by: York Sun --- Changes in v3: None Changes in v2: None arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 8 include/configs/ls2080a_common.h | 1 - scripts/config_whitelist.txt

[U-Boot] [PATCH v3 11/11] armv8: layerscape: Update early MMU for DDR after initialization

In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun --- Changes

[U-Boot] [PATCH v3 08/11] armv8: layerscape: Fix the sequence of changing MMU table

This patch follows the break-before-make process when making changes to MMU table. MMU is disabled before changing TTBR to avoid any potential race condition. Signed-off-by: York Sun --- Changes in v3: Instead of flushing d-cache, following the break-before-make process to change MMU table.

[U-Boot] [PATCH v3 05/11] armv8: layerscape: Rewrite memory reservation

For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank siz

[U-Boot] [PATCH v3 07/11] armv8: layerscape: Update MMU mapping with actual DDR size

Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access. Signed-off-by: York Sun --- Changes in v3: None Changes in v2: None arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 42 +++-- 1 file changed, 40 i

[U-Boot] [PATCH v3 10/11] armv8: mmu: Add a function to change mapping attributes

Function mmu_change_region_attr() is added to change existing mapping with updated PXN, UXN and memory type. This is a break-before-make process during which the mapping becomes fault (invalid) before final attributres are set. Signed-off-by: York Sun --- Changes in v3: None Changes in v2: None

[U-Boot] [PATCH v3 06/11] driver: net: fsl-mc: Update calculation of MC RAM

Since the reserved RAM is tracked by gd->arch.resv_ram, calculation of MC memory blocks can be simplified. The MC RAM is guaranteed to be aligned by the reservation process. Signed-off-by: York Sun CC: Priyanka Jain --- Changes in v3: None Changes in v2: None drivers/net/fsl-mc/mc.c | 59

Re: [U-Boot] arm: cache: misaligned operation with fastboot

Hi Gary, On Wed, Mar 1, 2017 at 12:12 PM, Gary Bisson wrote: > Hi Fabio, Lukasz, > > On Wed, Feb 15, 2017 at 02:24:40PM -0200, Fabio Estevam wrote: >> On Wed, Feb 15, 2017 at 2:04 PM, Gary Bisson >> wrote: >> > Hi, >> > >> > I've been testing fastboot to flash a sparse image on a i.MX6Q platform

Re: [U-Boot] [PATCH v3 08/11] armv8: layerscape: Fix the sequence of changing MMU table

On 03/01/2017 11:32 AM, York Sun wrote: > This patch follows the break-before-make process when making changes > to MMU table. MMU is disabled before changing TTBR to avoid any > potential race condition. > > Signed-off-by: York Sun > > --- > > Changes in v3: > Instead of flushing d-cache, follo

[U-Boot] [PATCH v3 03/11] armv8: ls2080a: Move CONFIG_SYS_MC_RSV_MEM_ALIGN to Kconfig

Use Kconfig option instead of config macro in header file. Signed-off-by: York Sun --- Changes in v3: None Changes in v2: None arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 8 include/configs/ls2080a_common.h | 1 - scripts/config_whitelist.txt | 1 - 3 files chang

[U-Boot] [PATCH v4 08/11] armv8: layerscape: Fix the sequence of changing MMU table

This patch follows the break-before-make process when making changes to MMU table. MMU is disabled before changing TTBR to avoid any potential race condition. Signed-off-by: York Sun --- Changes in v4: Revert the change of C bit in v3 patch. Changes in v3: Instead of flushing d-cache, foll

[U-Boot] [PATCH v4] armv8: spl: Call spl_relocate_stack_gd for ARMv8

As part of the startup process for boards using the SPL, we need to call spl_relocate_stack_gd. This is needed to set up malloc with its DRAM buffer. Signed-off-by: Philipp Tomsich Reviewed-by: Andre Przywara Reviewed-by: Simon Glass --- arch/arm/lib/crt0_64.S | 14 -- 1 file chang

[U-Boot] [PATCH v3 0/3] disk: efi: allow gap before partition entries

Motivated by the the SPL layout for SD/MMC devices on Allwinner SoCs (the SPL code needs to reside an 8K offset into the device), we add support for leaving a gap between the MBR (LBA#0), GPT header (LBA#1) and GPT partition entries (linked from field in the GPT header). Changes in v2: * CONFIG_E

[U-Boot] [PATCH v3 1/3] part_efi: support padding between the GPT header and partition entries

Some architectures require their SPL loader at a fixed address within the first 16KB of the disk. To avoid an overlap with the partition entries of the EFI partition table, the first safe offset (in bytes, from the start of the device) for the entries can be set through CONFIG_EFI_PARTITION_ENTRIES

[U-Boot] [PATCH v3 2/3] doc: move documentation for /config node into a separate file

This moves the description of the /config node from README.fdt-control into a separate file doc/device-tree-bindings/config.txt. Signed-off-by: Philipp Tomsich Reviewed-by: Simon Glass --- doc/README.fdt-control | 16 doc/device-tree-bindings/config.txt | 14 ++

[U-Boot] [PATCH v3 3/3] part_efi: document device-tree binding for part_efi configuration

This adds documentation on the u-boot,efi-partition-entries-offset property (which overrides CONFIG_EFI_PARTITION_ENTRIES_OFF, if present). Signed-off-by: Philipp Tomsich Reviewed-by: Simon Glass --- doc/device-tree-bindings/config.txt | 8 1 file changed, 8 insertions(+) diff --git a

[U-Boot] [PATCH v3 1/9] sunxi: add pinctrl (UCLASS_PINCTRL) support for sunxi

This change adds a full device-model pinctrl driver for sunxi (tested with sun50iw1p1) based on the support available in Linux. Details are: * implements a driver for pinctrl devices and assigns sun50i-a64-pinctrl and sun50i-a64-r-pinctrl to it * dynamically creates the driver_data for a sunx

[U-Boot] [PATCH v3 3/9] sunxi: CONFIG_DM_ALLOW_MULTIPLE_DRIVERS for gpio/pinctrl binding

Our gpio and pinctrl driver need to be bound against the same node. While this can be done by hand (i.e. explicitly looking up the driver, creating the driver-data and binding the device), it is much easier done when the new option for the binding of multiple drivers against a single node is config

[U-Boot] [PATCH v3 4/9] Kconfig: sunxi: Select new option for allow multiple drivers to bind

For pinctrl & gpio and reset & clk, the sunxi (Allwinner SoC) board support needs to bind multiple drivers to a single DT node. Select the necessary config-option when selecting ARCH_SUNXI. Signed-off-by: Philipp Tomsich --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/a

[U-Boot] [PATCH v3 5/9] sunxi: add module reset (UCLASS_RESET) support for sunxi

In order to have the device model describe the module reset bits on sunxi (well, at least for anything newer than sun6i), we need a (rather simple) driver for 'allwinner,sun6i-a31-clock-reset' nodes. Signed-off-by: Philipp Tomsich --- drivers/reset/Kconfig | 9 ++ drivers/

[U-Boot] [PATCH v3 2/9] dm: core: Allow multiple drivers to bind for a single node

Currently, driver binding stops once it encounters the first compatible driver that doesn't refuse to bind. However, there are cases where a single node will need to be handled by multiple driver classes. For those cases we provide a configurable option to continue to bind after the first driver ha

[U-Boot] [PATCH v3 7/9] clk: clk-uclass: add clk_get_by_output_name

Signed-off-by: Philipp Tomsich --- drivers/clk/clk-uclass.c | 30 ++ include/clk.h| 22 ++ 2 files changed, 52 insertions(+) diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 6fcfd69..a6a65b2 100644 --- a/drivers/cl

[U-Boot] [PATCH v3 6/9] linux/kernel.h: sync DIV_ROUND_UP_ULL from kernel

The DIV_ROUND_UP_ULL is required for porting the sunxi clock (CCU) binding from linux. --- include/linux/kernel.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/linux/kernel.h b/include/linux/kernel.h index 0b61671..dc3f36a 100644 --- a/include/linux/kernel.h +++ b/include/linux/ker

[U-Boot] [PATCH v3 0/9] sunxi: DM-based CLK, RESET and PINCTRL

Hi everyone, here's the the new version of CLK, RESET and PINCTRL drivers to configure sunxi from the device-tree. This adds support for the upstream CCU node (for reset and pinctrl) and tries to address the various concerns people had. Note that (to stay in sync with the Linux files), some of t

[U-Boot] [PATCH v3 9/9] cmd: move CONFIG_CMD_CLK to Kconfig

The CMD_CLK configuration allows the clk-command today (having only the 'clk dump' action for printing the clock configuration using a per-SoC weak function). It is currently only selected by ZYNC and PIC32. To make it easier to use this command for other platforms and to select it via defconfig,

Re: [U-Boot] [PATCH 1/2 RFT] sunxi: power: Add AXP806 and AXP808 support

On Mon, Feb 27, 2017 at 11:26:33AM +0800, Chen-Yu Tsai wrote: > On Mon, Feb 27, 2017 at 3:01 AM, Rask Ingemann Lambertsen > wrote: > > An X-Powers AXP806 or AXP808 PMIC is usually found on boards using the > > Allwinner A80 ARM SoC. This patch adds support for the PMIC's regulators > > and sets up

[U-Boot] [PATCH v2 0/2] sunxi: DM-based driver for SPI

A new iteration of the dual-IO aware device-model based SPI driver for sunxi (Allwinner SoCs). As before, this has been tested with dual-IO flashes (Winbond W25Q80DV) on our A64-uQ7 at up to 100MHz. Changes in v2: * Uses wait_bit instead of readl_poll_... for better readability * To address Jag

[U-Boot] [PATCH v2 1/2] spi: sunxi_spi: Add DM SPI driver for A31/A80/A64

This adds a rewrite of the SPI driver we had in use for the A31-uQ7 (sun6i), A80-Q7 (sun9i) and A64-uQ7 (sun50i) boards, which includes support for: * cs-gpios (i.e. GPIOs as additional chip-selects) * clocking, reset and pinctrl based on the device-model * dual-IO data receive for controllers t

[U-Boot] [PATCH v2 2/2] sunxi_spi: add support for dual-IO flashes

The SPI controller in the Allwinner A64 SoC supports dual-IO for the RX phase of transmission. This can be used with the command 'fast read dual output' (cmd, addr and dummy byte are transmitted in single-IO mode; data is received in dual-IO mode) to quickly read out SPI flashes, when the device-t

[U-Boot] [PATCH v1] i2c: sunxi: add device-model support for i2c

The I2C block in sunxi (Allwinner SoCs) is based on Designware and uses the same driver as the Marvell Orion 5x and Kirkwood families. This change adds a compatible id matching the binding for sunxi devices, supports configuring the clocks and to release the module reset on sunxi platforms as dire

[U-Boot] [PATCHv2 2/3] FIT: Rename FIT_DISABLE_SHA256 to FIT_ENABLE_SHA256_SUPPORT

We rename CONFIG_FIT_DISABLE_SHA256 to CONFIG_FIT_ENABLE_SHA256_SUPPORT which is enabled by default and now a positive option. Convert the handful of boards that were disabling it before to save space. Cc: Dirk Eibach Cc: Lukasz Dalek Signed-off-by: Tom Rini --- Changes in v2: New patch Kco

[U-Boot] [PATCHv2 3/3] lib: move hash CONFIG options to Kconfig

From: Masahiro Yamada Commit 94e3c8c4fd7b ("crypto/fsl - Add progressive hashing support using hardware acceleration.") created entries for CONFIG_SHA1, CONFIG_SHA256, CONFIG_SHA_HW_ACCEL, and CONFIG_SHA_PROG_HW_ACCEL. However, no defconfig has migrated to it. Complete the move with moveconfig t

Re: [U-Boot] [PATCH v2 6/8] dts: socfpga: Add trigger-address property to QSPI device

Hi Jason, On 03/01/2017 10:38 AM, Rush, Jason A. wrote: > Add the 'cdns,trigger-address' property to the cadence QSPI device > node for Altera SoC devices. > > Signed-off-by: Jason A. Rush > --- > Changed in v2: > - renamed trigger-base to trigger-address > > arch/arm/dts/socfpga.dtsi | 1 + >

Re: [U-Boot] [PATCH v2 6/8] dts: socfpga: Add trigger-address property to QSPI device

Dinh Nguyen wrote: > Hi Jason, > > On 03/01/2017 10:38 AM, Rush, Jason A. wrote: >> Add the 'cdns,trigger-address' property to the cadence QSPI device >> node for Altera SoC devices. >> >> Signed-off-by: Jason A. Rush >> --- >> Changed in v2: >> - renamed trigger-base to trigger-address >> >> a

Re: [U-Boot] [PATCH v2 6/8] dts: socfpga: Add trigger-address property to QSPI device

On 03/01/2017 05:07 PM, Rush, Jason A. wrote: > Dinh Nguyen wrote: >> Hi Jason, >> >> On 03/01/2017 10:38 AM, Rush, Jason A. wrote: >>> Add the 'cdns,trigger-address' property to the cadence QSPI device >>> node for Altera SoC devices. >>> >>> Signed-off-by: Jason A. Rush >>> --- >>> Changed in

Re: [U-Boot] i.MX6QP sd boot issue

> -Original Message- > From: Jagan Teki [mailto:ja...@openedev.com] > Sent: Wednesday, March 01, 2017 10:12 PM > To: Peng Fan > Cc: Jagan Teki ; u-boot@lists.denx.de > Subject: Re: [U-Boot] i.MX6QP sd boot issue > > On Wed, Mar 1, 2017 at 6:28 PM, Peng Fan wrote: > > Hi Jagan, > > > >

Re: [U-Boot] [PATCHv2 3/3] lib: move hash CONFIG options to Kconfig

Hi Tom, 2017-03-02 6:52 GMT+09:00 Tom Rini : > From: Masahiro Yamada > > Commit 94e3c8c4fd7b ("crypto/fsl - Add progressive hashing support > using hardware acceleration.") created entries for CONFIG_SHA1, > CONFIG_SHA256, CONFIG_SHA_HW_ACCEL, and CONFIG_SHA_PROG_HW_ACCEL. > However, no defconfi

Re: [U-Boot] [PATCHv2 3/3] lib: move hash CONFIG options to Kconfig

On Thu, Mar 02, 2017 at 10:35:53AM +0900, Masahiro Yamada wrote: > Hi Tom, > > > 2017-03-02 6:52 GMT+09:00 Tom Rini : > > From: Masahiro Yamada > > > > Commit 94e3c8c4fd7b ("crypto/fsl - Add progressive hashing support > > using hardware acceleration.") created entries for CONFIG_SHA1, > > CONFI

[U-Boot] [PATCH] powerpc: e6500: Lock/unlock 1 cache instead of L1 as init_ram

Fir E6500 cores, L2 cache has been used as init_ram. L1 cache is a write through cache on E6500.If lines are not locked in both L1 and L2 caches, crashes are observed during secure boot. This patch locks/unlocks both L1 as well as L2 cache to prevent the crash. Signed-off-by: Ruchika Gupta --- a

[U-Boot] [PATCH] powerpc: e6500: Lock/unlock 1 cache instead of L1 as init_ram

Fir E6500 cores, L2 cache has been used as init_ram. L1 cache is a write through cache on E6500.If lines are not locked in both L1 and L2 caches, crashes are observed during secure boot. This patch locks/unlocks both L1 as well as L2 cache to prevent the crash. Signed-off-by: Ruchika Gupta --- a

Re: [U-Boot] [PATCH 07/10] sunxi: Convert CONFIG_RGMII to Kconfig

Hi Thomas, On Mon, Feb 27, 2017 at 02:59:46PM +0100, Thomas Petazzoni wrote: > Hello, > > On Thu, 23 Feb 2017 16:44:16 +0100, Mylène Josserand wrote: > > Convert CONFIG_RGMII to Kconfig. Thanks to that, it is possible to > > update defconfig files of SYS_EXTRA_OPTIONS accordingly and > > remove i

Re: [U-Boot] [linux-sunxi] Re: [PATCH v2] sunxi: add NanoPi NEO Air defconfig

On 03/01/17 at 03:33pm, Chen-Yu Tsai wrote: > On Sat, Feb 25, 2017 at 4:26 PM, Jagan Teki wrote: > > On Mon, Feb 13, 2017 at 1:22 PM, Maxime Ripard > > wrote: > >> On Sun, Feb 12, 2017 at 04:21:40PM +0100, Jelle van der Waa wrote: > >>> Add support for the NanoPi NEO Air H3 board from friendlyarm

Re: [U-Boot] [PATCH v4 3/7] usb: host: xhci-omap: fix double weak board_usb_init functions

On 02/28/2017 03:13 PM, Roger Quadros wrote: On 28/02/17 10:00, Uri Mashiach wrote: Hi, On 02/27/2017 06:22 PM, Roger Quadros wrote: Hi, On 23/02/17 15:39, Uri Mashiach wrote: A weak version of the function board_usb_init is implemented in: common/usb.c drivers/usb/host/xhci-omap.c [...]

Re: [U-Boot] [PATCH] sunxi: Add boards/sunxi and arch/arm/mach-sunxi to sunxi MAINTAINERS entry

On Wed, Mar 1, 2017 at 11:33 AM, Chen-Yu Tsai wrote: > Recently some sunxi related code was moved to arch/arm/mach-sunxi, but > the MAINTAINERS entry was not updated to reflect this. Add this, and > the board level boards/sunxi directory to our entry. > > While at it, also update its status, to re

Re: [U-Boot] [linux-sunxi] [PATCH 00/12] sunxi: Add support for R40 SoC

2017年3月1日 15:04于 Chen-Yu Tsai 写道： > > Hi everyone, > > This series adds support for the new R40 SoC. The R40 is marketed as the > successor to the A20. It is mostly pin compatible (in software) with the > A20. It has a somewhat similar memory layout, a hybrid of A20 and newer > sun6i gen.. Lik

[U-Boot] [RFC PATCH 1/3] dm: core: Add pre-OS remove flag to device_remove()

This patch adds the pre_os_remove boolean flag to device_remove() and changes all calls to this function to provide the default value of "false". This is in preparation for the driver specific pre-OS remove support. Signed-off-by: Stefan Roese Cc: Simon Glass --- arch/x86/cpu/queensbay/tnc.c

[U-Boot] [RFC PATCH 3/3] arm: bootm: Add dm_pre_os_remove() call to announce_and_cleanup()

This patch adds a call to dm_pre_os_remove() to announce_and_cleanup() so that drivers that have the flag DM_FLAG_PRE_OS_REMOVE set may do some last-stage cleanup before the OS is started. Signed-off-by: Stefan Roese Cc: Simon Glass --- arch/arm/lib/bootm.c | 8 1 file changed, 8 inser

[U-Boot] [RFC PATCH 2/3] dm: core: Add dm_pre_os_remove() and hook it into device_remove()

The new function dm_pre_os_remove() is intented for driver specific last-stage cleanup operations before the OS is started. This patch adds this functionality and hooks it into the common device_remove() function. To enable usage for custom driver (e.g. ethernet drivers), this patch also sets the

Re: [U-Boot] [PATCH] sunxi: makes an invisible option for H3-like DRAM controllers

On Tue, Feb 14, 2017 at 7:19 PM, Icenowy Zheng wrote: > Allwinner SoCs after H3 (e.g. A64, H5, R40, V3s) uses a H3-like > DesignWare DRAM controller, which do not have official free DRAM > initialization code, but can use modified dram_sun8i_h3.c. > > Add a invisible option for easier DRAM initial

Re: [U-Boot] [PATCH v2 1/6] sunxi: add invisible options for PRCM and RSB support

On Sun, Feb 26, 2017 at 5:22 AM, Icenowy Zheng wrote: > The Makefile of mach-sunxi used to build PRCM and RSB according to the > SoC's MACH_SUNxI macro, which makes it needed to add lines for new SoC > generation. > > Change this behavior to invisible options in sunxi Kconfig, so that new > lines

Re: [U-Boot] [PATCH v2 3/6] sunxi: add AXP_PMIC_BUS invisible options for AXP PMICs access

On Sun, Feb 26, 2017 at 5:22 AM, Icenowy Zheng wrote: > For AXP PMICs' drivers some functions are needed to provide I/O access > for the PMIC. > > The source file used to be controlled by different AXPxxx_POWER config > option. > > Control the file's compliation via a generic AXP_PMIC_BUS option,

Re: [U-Boot] Device cleanup before starting OS (Linux)

Hi Simon, On 01.03.2017 06:52, Stefan Roese wrote: On 01.03.2017 06:40, Simon Glass wrote: On 28 February 2017 at 09:32, Stefan Roese wrote: Hi! I'm currently trying to add some code to stop (DMA) buffer usage in the Marvell mvpp2 ethernet driver, that should only be executed once, before t

Re: [U-Boot] [PATCH 01/12] sunxi: Add initial support for R40

Hi Chen-Yu On Wed, Mar 01, 2017 at 03:04:36PM +0800, Chen-Yu Tsai wrote: > The R40 is the successor to the A20. It is a hybrid of the A20, A33 > and the H3. > > The R40's PIO controller is compatible with the A20, > Reuse the A20 UART and I2C muxing code by adding the R40's macro. > > The displa

Re: [U-Boot] [PATCH 02/12] sunxi: Enable AXP221s in I2C mode with the R40 SoC

On Wed, Mar 01, 2017 at 03:04:37PM +0800, Chen-Yu Tsai wrote: > The R40 SoC uses the AXP221s in I2C mode to supply power. > > Some regulator's common usages have changed, and also the recommended > voltage for existing usages have changed. Update the defaults to match. > > Signed-off-by: Chen-Yu

Re: [U-Boot] [PATCH 04/12] sunxi: Add mmc[1-3] pinmux settings for R40

On Wed, Mar 01, 2017 at 03:04:39PM +0800, Chen-Yu Tsai wrote: > The PIO is generally compatible with the A20, except that it routes the > full 8 bits and eMMC reset pins for mmc2. > > Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded

Re: [U-Boot] [PATCH 03/12] sunxi: Fix watchdog reset function for R40

On Wed, Mar 01, 2017 at 03:04:38PM +0800, Chen-Yu Tsai wrote: > The watchdog found on the R40 SoC is the older variant found on the A20. > Add the proper "#if defines" to make it work. > > Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard Thanks! Maxime -- Maxime Ripard, Free Electrons Emb

Re: [U-Boot] [PATCH 01/12] sunxi: Add initial support for R40

On Wed, Mar 1, 2017 at 6:55 PM, Maxime Ripard wrote: > Hi Chen-Yu > > On Wed, Mar 01, 2017 at 03:04:36PM +0800, Chen-Yu Tsai wrote: >> The R40 is the successor to the A20. It is a hybrid of the A20, A33 >> and the H3. >> >> The R40's PIO controller is compatible with the A20, >> Reuse the A20 UART

Re: [U-Boot] [PATCH] spi: cadence_qspi_apb: Add trigger-base DT bindings from Linux

On Tuesday 28 February 2017 10:36 PM, Rush, Jason A. wrote: > R, Vignesh wrote: >> On 2/28/2017 8:38 PM, Rush, Jason A. wrote: >> [...] >>> >>> This also works. >>> >>> Marek - how do you feel about a patch series with the following: >>> >>> 1. revert commit 57897c13de03ac0136d64641a3eab526c68103

[U-Boot] [PATCH 0/8] Stop AXP from crashing when enabeling LDO3

Hi list, When powering up an AXP209, the default value for LDO3 output is enabled. This works fine. However if for whatever reason, LDO3 is disabled, for example by OS during reboot and u-boot enables LDO3 again, the PMIC shutsdown (without setting an interrupt) causing the board to hang. This beh

[U-Boot] [PATCH 1/8] sunxi: board: Print error after power initialization fails

Currently during init, we enable all power, then enable the dram and after that check if there was an error during power-up. This makes little sense, we should enable power and then check if power was brought up properly initializing other things. This patch moves the DRAM init after the power fa

[U-Boot] [PATCH 2/8] sunxi: pmic_bus: Decrease boot time by not writing duplicate data

When we set or clear a pmic_bus bit, we do a read-modify-write operation. We waste some time however, by writing back the exact same value that was already set in the chip. Let us thus only configure the chip if the data is different. Signed-off-by: Olliver Schinagl --- arch/arm/mach-sunxi/pmic_

[U-Boot] [PATCH 3/8] power: axp209: Use BIT() macro

Use the standard BIT() macro to define BITS. Signed-off-by: Olliver Schinagl --- include/axp209.h | 34 ++ 1 file changed, 18 insertions(+), 16 deletions(-) diff --git a/include/axp209.h b/include/axp209.h index e1b22e3442..7803300328 100644 --- a/include/axp209.

Re: [U-Boot] [PATCH] drivers/usb/ehci: Use platform-specific accessors

Hi Marek, On Fri, 2017-02-10 at 21:33 +0100, Marek Vasut wrote: > On 02/10/2017 09:23 PM, Alexey Brodkin wrote: > > > > Current implementation doesn't allow utilization of platform-specific > > reads and writes. > > > > But some arches or platforms may want to use their accessors that do > > som

[U-Boot] [PATCH 8/8] arm: sunxi: Enable inrush quirk on Olimex OLinuXino-A20-Lime2

The lime2 features a too large capacitor on the LDO3 output, which causes the PMIC to shutdown when enabling power. To be able to still boot up however, we must gradually enable power on LDO3 for this board. Signed-off-by: Olliver Schinagl --- configs/A20-OLinuXino-Lime2_defconfig | 1 + 1 file

[U-Boot] [PATCH 7/8] power: axp209: Limit inrush current for broken boards

Some boards feature a capacitance on LDO3's output that is to large, causing inrush currents which as a result, shut down the AXP209. This has been reported before, without knowing the actual cause. A fix appeared to be done with commit 0e6e34ac8db ("sunxi: Olimex A20 boards: Enable LDO3 and LDO4

[U-Boot] [PATCH 4/8] power: axp209: Define the chip version mask

Use a define for the chip version mask on the axp209. Signed-off-by: Olliver Schinagl --- drivers/power/axp209.c | 5 + include/axp209.h | 2 ++ 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/power/axp209.c b/drivers/power/axp209.c index 731b75e50a..d496f675a1 1

[U-Boot] [PATCH 5/8] power: axp209: Reduce magic values by adding defines for LDO[234]

The AXP209 has a few 'magisc-ish' values that are better served with clear defines. Signed-off-by: Olliver Schinagl --- drivers/power/axp209.c | 10 -- include/axp209.h | 14 ++ 2 files changed, 18 insertions(+), 6 deletions(-) diff --git a/drivers/power/axp209.c b/dri

[U-Boot] [PATCH 6/8] power: axp209: Add support for voltage rate control on LDO3

The AXP209 has voltage rate control, or can set a slew rate, for LDO3. This allows for the power to gradually rise to the desired voltage, instead of spiking up quickly. Reason to have this can be to reduce the inrush currents for example. There are 3 slopes to choose from, the default, 'none' is

Re: [U-Boot] i.MX6QP sd boot issue

+ ML On Wed, Mar 1, 2017 at 6:23 PM, Jagan Teki wrote: > Hi Peng and All, > > I'm trying to boot from SD, on imx6qplus sabre board. > > - SW6: D1-D8 => 0100 0010 > - SD card on SD3 > - D12 with USB-to-Serial 115200 8N1 > - Power supply Output 5V > > Build: > $ make mx6qpsabreauto_defconfig; make

Re: [U-Boot] i.MX6QP sd boot issue

Hi Jagan, Did you put J3 to connect 1-2? Jumper Boot Selection 1 - 2 Do not boot from SPI NOR (default) 2 - 3 Boot from SPI NOR > -Original Message- > From: Jagan Teki [mailto:ja...@openedev.com] > Sent: Wednesday, March 01, 2017 8:56 PM > To: u-boot@lists.denx.de > Cc: Peng Fan ; Stefa

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