In order to have the device model describe the module reset bits
on sunxi (well, at least for anything newer than sun6i), we need
a (rather simple) driver for 'allwinner,sun6i-a31-clock-reset'
nodes.
Signed-off-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
---
drivers/reset/Kconfig | 9 ++
drivers/reset/Makefile | 1 +
drivers/reset/sunxi/Makefile | 6 ++
drivers/reset/sunxi/ccu-sun50i-a64.c | 75 +++++++++++++
drivers/reset/sunxi/ccu_reset.h | 9 ++
drivers/reset/sunxi/reset-sunxi.c | 168 +++++++++++++++++++++++++++++
include/dt-bindings/reset/sun50i-a64-ccu.h | 98 +++++++++++++++++
7 files changed, 366 insertions(+)
create mode 100644 drivers/reset/sunxi/Makefile
create mode 100644 drivers/reset/sunxi/ccu-sun50i-a64.c
create mode 100644 drivers/reset/sunxi/ccu_reset.h
create mode 100644 drivers/reset/sunxi/reset-sunxi.c
create mode 100644 include/dt-bindings/reset/sun50i-a64-ccu.h
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index c42b0bc..8db25fc 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -43,4 +43,13 @@ config RESET_UNIPHIER
Say Y if you want to control reset signals provided by System Control
block, Media I/O block, Peripheral Block.
+config RESET_SUNXI
+ bool "Reset controller driver for Allwiner SoCs"
+ depends on DM_RESET && ARCH_SUNXI
+ default y
+ help
+ Support for reset controllers on Allwinner SoCs.
+ Say Y if you want to control reset signals provided by CCU (e.g.
sun50i)
+ or PRCM (e.g. sun6i, sun9i) blocks.
+
endmenu
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 5c4305c..a4994e9 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o
obj-$(CONFIG_TEGRA_CAR_RESET) += tegra-car-reset.o
obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
+obj-$(CONFIG_RESET_SUNXI) += sunxi/
diff --git a/drivers/reset/sunxi/Makefile b/drivers/reset/sunxi/Makefile
new file mode 100644
index 0000000..559c79a
--- /dev/null
+++ b/drivers/reset/sunxi/Makefile
@@ -0,0 +1,6 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += reset-sunxi.o
+obj-$(CONFIG_MACH_SUN50I) += ccu-sun50i-a64.o
\ No newline at end of file
diff --git a/drivers/reset/sunxi/ccu-sun50i-a64.c
b/drivers/reset/sunxi/ccu-sun50i-a64.c
new file mode 100644
index 0000000..f7c388e
--- /dev/null
+++ b/drivers/reset/sunxi/ccu-sun50i-a64.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * The tabular data contained in this file is reused verbatim from
+ * Linux (drivers/clk/sunxi-ng.c), which is:
+ * Copyright (c) 2016 Maxime Ripard. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+
+#include <common.h>
+#include <dt-bindings/reset/sun50i-a64-ccu.h>
+
+#include "ccu_reset.h"
+
+const struct ccu_reset_map sun50i_a64_ccu_resets[] = {
+ [RST_USB_PHY0] = { 0x0cc, BIT(0) },
+ [RST_USB_PHY1] = { 0x0cc, BIT(1) },
+ [RST_USB_HSIC] = { 0x0cc, BIT(2) },
+
+ [RST_DRAM] = { 0x0f4, BIT(31) },
+ [RST_MBUS] = { 0x0fc, BIT(31) },
+
+ [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },
+ [RST_BUS_CE] = { 0x2c0, BIT(5) },
+ [RST_BUS_DMA] = { 0x2c0, BIT(6) },
+ [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
+ [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
+ [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
+ [RST_BUS_NAND] = { 0x2c0, BIT(13) },
+ [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
+ [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
+ [RST_BUS_TS] = { 0x2c0, BIT(18) },
+ [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
+ [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
+ [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
+ [RST_BUS_OTG] = { 0x2c0, BIT(23) },
+ [RST_BUS_EHCI0] = { 0x2c0, BIT(24) },
+ [RST_BUS_EHCI1] = { 0x2c0, BIT(25) },
+ [RST_BUS_OHCI0] = { 0x2c0, BIT(28) },
+ [RST_BUS_OHCI1] = { 0x2c0, BIT(29) },
+
+ [RST_BUS_VE] = { 0x2c4, BIT(0) },
+ [RST_BUS_TCON0] = { 0x2c4, BIT(3) },
+ [RST_BUS_TCON1] = { 0x2c4, BIT(4) },
+ [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
+ [RST_BUS_CSI] = { 0x2c4, BIT(8) },
+ [RST_BUS_HDMI0] = { 0x2c4, BIT(10) },
+ [RST_BUS_HDMI1] = { 0x2c4, BIT(11) },
+ [RST_BUS_DE] = { 0x2c4, BIT(12) },
+ [RST_BUS_GPU] = { 0x2c4, BIT(20) },
+ [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
+ [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
+ [RST_BUS_DBG] = { 0x2c4, BIT(31) },
+
+ [RST_BUS_LVDS] = { 0x2c8, BIT(0) },
+
+ [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
+ [RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
+ [RST_BUS_THS] = { 0x2d0, BIT(8) },
+ [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
+ [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
+ [RST_BUS_I2S2] = { 0x2d0, BIT(14) },
+
+ [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
+ [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
+ [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
+ [RST_BUS_SCR] = { 0x2d8, BIT(5) },
+ [RST_BUS_UART0] = { 0x2d8, BIT(16) },
+ [RST_BUS_UART1] = { 0x2d8, BIT(17) },
+ [RST_BUS_UART2] = { 0x2d8, BIT(18) },
+ [RST_BUS_UART3] = { 0x2d8, BIT(19) },
+ [RST_BUS_UART4] = { 0x2d8, BIT(20) },
+};
diff --git a/drivers/reset/sunxi/ccu_reset.h b/drivers/reset/sunxi/ccu_reset.h
new file mode 100644
index 0000000..83b30a0
--- /dev/null
+++ b/drivers/reset/sunxi/ccu_reset.h
@@ -0,0 +1,9 @@
+#ifndef _CCU_RESET_H_
+#define _CCU_RESET_H_
+
+struct ccu_reset_map {
+ uint16_t reg;
+ uint32_t bit;
+};
+
+#endif /* _CCU_RESET_H_ */
diff --git a/drivers/reset/sunxi/reset-sunxi.c
b/drivers/reset/sunxi/reset-sunxi.c
new file mode 100644
index 0000000..8fbfa85
--- /dev/null
+++ b/drivers/reset/sunxi/reset-sunxi.c
@@ -0,0 +1,168 @@
+/*
+ * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <reset-uclass.h>
+#include <dm/device.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+
+#include "ccu_reset.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct sunxi_reset_priv {
+ void *base;
+ size_t size;
+};
+
+static int sunxi_reset_request(struct reset_ctl *reset_ctl)
+{
+ debug("%s (%s): id %ld\n",
+ reset_ctl->dev->name, __func__, reset_ctl->id);
+ return 0;
+}
+
+static int sunxi_reset_free(struct reset_ctl *reset_ctl)
+{
+ debug("%s (%s): id %ld\n",
+ reset_ctl->dev->name, __func__, reset_ctl->id);
+ return 0;
+}
+
+static int sunxi_reset_update_bit(struct udevice *dev,
+ const uint32_t off,
+ const uint32_t bitmask,
+ const bool assert)
+{
+ const struct sunxi_reset_priv *priv = dev_get_priv(dev);
+
+ debug("%s (%s): base %p offset %x bit %x assert %d size %ld\n",
+ dev->name, __func__,
+ priv->base, off, bitmask, assert, priv->size);
+
+ if (off >= priv->size)
+ return -EINVAL;
+
+ if (assert)
+ clrbits_le32(priv->base + off, bitmask);
+ else
+ setbits_le32(priv->base + off, bitmask);
+
+ return 0;
+}
+
+static int sunxi_ccu_reset_update(struct reset_ctl *reset_ctl, bool assert)
+{
+ struct udevice *dev = reset_ctl->dev;
+ const struct ccu_reset_map *reset_map =
+ (const struct ccu_reset_map *)dev_get_driver_data(dev);
+ const struct ccu_reset_map *entry = &reset_map[reset_ctl->id];
+
+ return sunxi_reset_update_bit(dev, entry->reg, entry->bit, assert);
+}
+
+static int sunxi_ccu_reset_assert(struct reset_ctl *reset_ctl)
+{
+ return sunxi_ccu_reset_update(reset_ctl, true);
+}
+
+static int sunxi_ccu_reset_deassert(struct reset_ctl *reset_ctl)
+{
+ return sunxi_ccu_reset_update(reset_ctl, false);
+}
+
+static int sunxi_reset_update(struct reset_ctl *reset_ctl, bool assert)
+{
+ struct udevice *dev = reset_ctl->dev;
+ const unsigned long id = reset_ctl->id;
+ const unsigned long offset = (id / 32) * sizeof(uint32_t);
+ const unsigned int bit = id % 32;
+
+ return sunxi_reset_update_bit(dev, offset, BIT(bit), assert);
+}
+
+static int sunxi_reset_assert(struct reset_ctl *reset_ctl)
+{
+ return sunxi_reset_update(reset_ctl, true);
+}
+
+static int sunxi_reset_deassert(struct reset_ctl *reset_ctl)
+{
+ return sunxi_reset_update(reset_ctl, false);
+}
+
+static int sunxi_reset_probe(struct udevice *dev)
+{
+ struct sunxi_reset_priv *priv = dev_get_priv(dev);
+ fdt_addr_t addr;
+ fdt_size_t size;
+
+ addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, dev->of_offset,
+ "reg", 0, &size, false);
+ if (addr == FDT_ADDR_T_NONE) {
+ debug("%s: failed to find base address ('reg')\n", dev->name);
+ return -ENODEV;
+ }
+ priv->base = (void *)addr;
+ priv->size = size;
+
+ if (!priv->base)
+ return -ENOMEM;
+
+ return 0;
+}
+
+static const struct reset_ops sunxi_reset_ops = {
+ .request = sunxi_reset_request,
+ .free = sunxi_reset_free,
+ .rst_assert = sunxi_reset_assert,
+ .rst_deassert = sunxi_reset_deassert,
+};
+
+static const struct udevice_id sunxi_reset_match[] = {
+ { .compatible = "allwinner,sun6i-a31-clock-reset" },
+ { }
+};
+
+
+U_BOOT_DRIVER(sunxi_reset) = {
+ .name = "sunxi-reset",
+ .id = UCLASS_RESET,
+ .of_match = sunxi_reset_match,
+ .ops = &sunxi_reset_ops,
+ .priv_auto_alloc_size = sizeof(struct sunxi_reset_priv),
+ .probe = sunxi_reset_probe,
+};
+
+static const struct reset_ops sunxi_ccu_reset_ops = {
+ .request = sunxi_reset_request,
+ .free = sunxi_reset_free,
+ .rst_assert = sunxi_ccu_reset_assert,
+ .rst_deassert = sunxi_ccu_reset_deassert,
+};
+
+#if defined(CONFIG_MACH_SUN50I)
+extern const struct ccu_reset_map sun50i_a64_ccu_resets;
+#endif
+
+static const struct udevice_id sunxi_ccu_reset_match[] = {
+#if defined(CONFIG_MACH_SUN50I)
+ { .compatible = "allwinner,sun50i-a64-ccu",
+ .data = (ulong)&sun50i_a64_ccu_resets },
+#endif
+ { }
+};
+
+U_BOOT_DRIVER(sunxi_ccu_reset) = {
+ .name = "sunxi-ccu-reset",
+ .id = UCLASS_RESET,
+ .of_match = sunxi_ccu_reset_match,
+ .ops = &sunxi_ccu_reset_ops,
+ .priv_auto_alloc_size = sizeof(struct sunxi_reset_priv),
+ .probe = sunxi_reset_probe,
+};
diff --git a/include/dt-bindings/reset/sun50i-a64-ccu.h
b/include/dt-bindings/reset/sun50i-a64-ccu.h
new file mode 100644
index 0000000..db60b29
--- /dev/null
+++ b/include/dt-bindings/reset/sun50i-a64-ccu.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2016 Maxime Ripard <maxime.rip...@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN50I_A64_H_
+#define _DT_BINDINGS_RST_SUN50I_A64_H_
+
+#define RST_USB_PHY0 0
+#define RST_USB_PHY1 1
+#define RST_USB_HSIC 2
+#define RST_DRAM 3
+#define RST_MBUS 4
+#define RST_BUS_MIPI_DSI 5
+#define RST_BUS_CE 6
+#define RST_BUS_DMA 7
+#define RST_BUS_MMC0 8
+#define RST_BUS_MMC1 9
+#define RST_BUS_MMC2 10
+#define RST_BUS_NAND 11
+#define RST_BUS_DRAM 12
+#define RST_BUS_EMAC 13
+#define RST_BUS_TS 14
+#define RST_BUS_HSTIMER 15
+#define RST_BUS_SPI0 16
+#define RST_BUS_SPI1 17
+#define RST_BUS_OTG 18
+#define RST_BUS_EHCI0 19
+#define RST_BUS_EHCI1 20
+#define RST_BUS_OHCI0 21
+#define RST_BUS_OHCI1 22
+#define RST_BUS_VE 23
+#define RST_BUS_TCON0 24
+#define RST_BUS_TCON1 25
+#define RST_BUS_DEINTERLACE 26
+#define RST_BUS_CSI 27
+#define RST_BUS_HDMI0 28
+#define RST_BUS_HDMI1 29
+#define RST_BUS_DE 30
+#define RST_BUS_GPU 31
+#define RST_BUS_MSGBOX 32
+#define RST_BUS_SPINLOCK 33
+#define RST_BUS_DBG 34
+#define RST_BUS_LVDS 35
+#define RST_BUS_CODEC 36
+#define RST_BUS_SPDIF 37
+#define RST_BUS_THS 38
+#define RST_BUS_I2S0 39
+#define RST_BUS_I2S1 40
+#define RST_BUS_I2S2 41
+#define RST_BUS_I2C0 42
+#define RST_BUS_I2C1 43
+#define RST_BUS_I2C2 44
+#define RST_BUS_SCR 45
+#define RST_BUS_UART0 46
+#define RST_BUS_UART1 47
+#define RST_BUS_UART2 48
+#define RST_BUS_UART3 49
+#define RST_BUS_UART4 50
+
+#endif /* _DT_BINDINGS_RST_SUN50I_A64_H_ */
--
1.9.1
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