Hi Dave,
> Good news, Good summary!
Thanks!
>> This testing revealed some interesting observations;
>>
>> 1) The Marvell 88E PHY generates a 125MHz output
>> clock that is used as the PowerPC EC_GTX_CLK125MHZ
>> clock source on the MDS board.
>>
>> The MDS board has to use the PH
Hi Dave,
Good news, Good summary!
> I modified the MPC8349E-MDS board and can create the
> same problem we were experiencing on our boards;
> CRC errors and data packets with received bytes
> repeated within the receive packets.
>
> So I am certain we have tracked the root cause of
> the problem
Hi all,
I modified the MPC8349E-MDS board and can create the
same problem we were experiencing on our boards;
CRC errors and data packets with received bytes
repeated within the receive packets.
So I am certain we have tracked the root cause of
the problem we were having with our boards.
The pr
Hi Dave,
>> I'm not ready to claim success, as I need to make the
>> change on other boards ... but its very encouraging!
>
> Good news, Dave.
> Sure, we need to keep the impedance matching.
> change the series resister.
> Anyway, I strong recommand you to check if the signal
> of GMII in
> Over the weekend we performed some hardware modifications
> on our boards with their troublesome gigabit interfaces.
>
> We performed a couple of tests, one of which may be
> the solution to our problem.
>
> 1) Modified the value of the series termination of EC_GTX_CLK125
>
> The PHY drive
Hi all,
Over the weekend we performed some hardware modifications
on our boards with their troublesome gigabit interfaces.
We performed a couple of tests, one of which may be
the solution to our problem.
1) Modified the value of the series termination of EC_GTX_CLK125
The PHY drives a 125MH
On Fri, 5 Jun 2009 19:31:06 -0700 (PDT)
d...@ovro.caltech.edu wrote:
> The bit setting did not help with our errors at
> 1Gbit, so the comment:
fixed and pushed onto mpc83xx master. regenerated patch below.
thanks for the clarification David.
Kim
mpc83xx: don't set SICRH_TSOBI1 to RMII/RTBI op
Hi Kim,
The bit setting did not help with our errors at
1Gbit, so the comment:
> While not making a difference on the MPC8349EMDS,
> changing the output buffer impedance on TSEC1 to
> 2.5V has negative effect on other mpc83xx based
> boards - they start dropping frame data
> consequently promptin
On Fri, 05 Jun 2009 14:45:38 -0400
Paul Gortmaker wrote:
> I applied the chunk below onto a checkout of v2009.06-rc2 and it
> works fine on sbc8349; tested both TSEC and at both 100 and 1GB.
>
> Tested-by: Paul Gortmaker
Thanks Paul, Ira, and Dave.
I've applied the following on u-boot-mpc83xx
Paul Gortmaker wrote:
> Kim Phillips wrote:
>> On Wed, 3 Jun 2009 10:50:25 -0700
>> Ira Snyder wrote:
>
> ...
>
>>>
>>> In practice, this doesn't seem to make a difference on the MPC8349EMDS
>>> eval board. Both settings work without any errors. For people like me,
>>> who are copying an existin
Kim Phillips wrote:
> On Wed, 3 Jun 2009 10:50:25 -0700
> Ira Snyder wrote:
...
>>
>> In practice, this doesn't seem to make a difference on the MPC8349EMDS
>> eval board. Both settings work without any errors. For people like me,
>> who are copying an existing board port to a similar board, it
Hi Dave,
>> The MPC8349EMDS config has had that setting since it was imported into
>> U-Boot. I've copied the relevant part of include/configs/MPC8349EMDS.h
>> below.
>>
>> #define CONFIG_SYS_SICRH SICRH_TSOBI1
>>
>> This seems wrong for the MPC8349EMDS board. I tried setting
>> the register
>> v
> The MPC8349EMDS config has had that setting since it was imported into
> U-Boot. I've copied the relevant part of include/configs/MPC8349EMDS.h
> below.
>
> #define CONFIG_SYS_SICRH SICRH_TSOBI1
>
> This seems wrong for the MPC8349EMDS board. I tried setting
> the register
> value to 0x0 by ha
On Wed, Jun 03, 2009 at 03:19:05PM -0500, Kim Phillips wrote:
> On Wed, 3 Jun 2009 10:50:25 -0700
> Ira Snyder wrote:
>
> > On Tue, Jun 02, 2009 at 06:08:17PM -0500, Kim Phillips wrote:
> > > On Tue, 2 Jun 2009 15:19:18 -0700
> > > Ira Snyder wrote:
> > >
> > > > On Tue, Jun 02, 2009 at 02:25:0
On Wed, 3 Jun 2009 10:50:25 -0700
Ira Snyder wrote:
> On Tue, Jun 02, 2009 at 06:08:17PM -0500, Kim Phillips wrote:
> > On Tue, 2 Jun 2009 15:19:18 -0700
> > Ira Snyder wrote:
> >
> > > On Tue, Jun 02, 2009 at 02:25:03PM -0700, Ira Snyder wrote:
> > > > >
> > > > > And what is the SICRH[30-31]
On Tue, Jun 02, 2009 at 06:08:17PM -0500, Kim Phillips wrote:
> On Tue, 2 Jun 2009 15:19:18 -0700
> Ira Snyder wrote:
>
> > On Tue, Jun 02, 2009 at 02:25:03PM -0700, Ira Snyder wrote:
> > > >
> > > > And what is the SICRH[30-31]?
> > > > Did you have the matching settings for GMII with 3.3V?
> >
On Tue, 2 Jun 2009 15:19:18 -0700
Ira Snyder wrote:
> On Tue, Jun 02, 2009 at 02:25:03PM -0700, Ira Snyder wrote:
> > >
> > > And what is the SICRH[30-31]?
> > > Did you have the matching settings for GMII with 3.3V?
> > >
> >
> > => md e118 1
> > e118: 0002
> >
> > This l
> Did you check the GMII interface (H/W)?
> Like EC_GTX_CLK125, this signal is input for TSEC block for
> 1000Mbps case.
> When you used the 100Mbps, the GTX_CLK125 is not used. Because you are
> Using the MII interface for 100Mbps case.
IIRC, the MV88E has some h/w config option to configure
> > => md e118 1
> > e118: 0002
> >
> > This looks wrong. The MPC8349EMDS board has the exact same
> setting in
> > that register. Writing 0x0 to the SICRH register did not cause the
> > problem to go away.
> >
>
> The MPC8349EMDS config has had that setting since it was imp
On Tue, Jun 02, 2009 at 02:25:03PM -0700, Ira Snyder wrote:
> >
> > And what is the SICRH[30-31]?
> > Did you have the matching settings for GMII with 3.3V?
> >
>
> => md e118 1
> e118: 0002
>
> This looks wrong. The MPC8349EMDS board has the exact same setting in
> that reg
Did you check the GMII interface (H/W)?
Like EC_GTX_CLK125, this signal is input for TSEC block for 1000Mbps
case.
When you used the 100Mbps, the GTX_CLK125 is not used. Because you are
Using the MII interface for 100Mbps case.
Thanks, Dave
___
U-Boot ma
On Wed, Jun 03, 2009 at 04:44:54AM +0800, Liu Dave-R63238 wrote:
> > What is the ACR register settings?
=> md e800 1
e800: 00030300
> > What is the freq of core/csb/DDR and TSEC block?
According to U-Boot's clocks command:
=> clocks
Clock configuration:
Core:533
> What is the ACR register settings?
> What is the freq of core/csb/DDR and TSEC block?
And what is the SICRH[30-31]?
Did you have the matching settings for GMII with 3.3V?
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What is the ACR register settings?
What is the freq of core/csb/DDR and TSEC block?
Thanks, Dave
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On Tue, Jun 02, 2009 at 08:50:04PM +0200, Wolfgang Denk wrote:
> Dear Ira Snyder,
>
> In message <20090602162757.ga6...@ovro.caltech.edu> you wrote:
> >
> > I've been working on a custom board, based heavily on the Freescale
> > MPC8349EMDS board. The only major difference is that the board has s
Hi Wolfgang,
>> I've been working on a custom board, based heavily on the Freescale
>> MPC8349EMDS board. The only major difference is that the board has some
>> FPGAs connected to the local bus.
>>
>> I've found that the TSEC / gianfar ethernet does not work for me in
>> 1000mbit mode. I constant
Dear Ira Snyder,
In message <20090602162757.ga6...@ovro.caltech.edu> you wrote:
>
> I've been working on a custom board, based heavily on the Freescale
> MPC8349EMDS board. The only major difference is that the board has some
> FPGAs connected to the local bus.
>
> I've found that the TSEC / gia
On Tue, 2 Jun 2009 11:17:26 -0700
Ira Snyder wrote:
> On Tue, Jun 02, 2009 at 12:35:14PM -0500, Peter Tyser wrote:
> > On Tue, 2009-06-02 at 09:42 -0700, David Hawkins wrote:
> > > > I am unable to reproduce the corruption on my MPC8349EMDS eval board,
> > > > but I'm running out of ideas to try
On Tue, Jun 02, 2009 at 12:35:14PM -0500, Peter Tyser wrote:
> On Tue, 2009-06-02 at 09:42 -0700, David Hawkins wrote:
> > > I am unable to reproduce the corruption on my MPC8349EMDS eval board,
> > > but I'm running out of ideas to try and find the source of this problem.
> >
> > One more piece o
Hi Peter,
>>> I am unable to reproduce the corruption on my MPC8349EMDS eval board,
>>> but I'm running out of ideas to try and find the source of this problem.
>> One more piece of info: the MPC8349E-MDS board contains the
>> MPC8349E processor, whereas our board contains the MPC8349EA
>> (silico
On Tue, 2009-06-02 at 09:42 -0700, David Hawkins wrote:
> > I am unable to reproduce the corruption on my MPC8349EMDS eval board,
> > but I'm running out of ideas to try and find the source of this problem.
>
> One more piece of info: the MPC8349E-MDS board contains the
> MPC8349E processor, where
> I am unable to reproduce the corruption on my MPC8349EMDS eval board,
> but I'm running out of ideas to try and find the source of this problem.
One more piece of info: the MPC8349E-MDS board contains the
MPC8349E processor, whereas our board contains the MPC8349EA
(silicon v 3.1) processor. We
Hello U-Boot users,
I've been working on a custom board, based heavily on the Freescale
MPC8349EMDS board. The only major difference is that the board has some
FPGAs connected to the local bus.
I've found that the TSEC / gianfar ethernet does not work for me in
1000mbit mode. I constantly get "go
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