On Tue, 2 Jun 2009 11:17:26 -0700 Ira Snyder <i...@ovro.caltech.edu> wrote:
> On Tue, Jun 02, 2009 at 12:35:14PM -0500, Peter Tyser wrote: > > On Tue, 2009-06-02 at 09:42 -0700, David Hawkins wrote: > > > > I am unable to reproduce the corruption on my MPC8349EMDS eval board, > > > > but I'm running out of ideas to try and find the source of this problem. > > > > > > One more piece of info: the MPC8349E-MDS board contains the > > > MPC8349E processor, whereas our board contains the MPC8349EA > > > (silicon v 3.1) processor. We did have a couple of MPC8349EA-MDS > > > boards, however, the Xilinx CPLD on both boards spontaneously > > > destructed (the CPLD sticky labels melted!). > > > > > > We can try putting the MPC8349EA processor from one of the > > > dead boards into the MPC8349E-MDS board socket - I believe > > > this is ok - feel free to warn us that its not :) the 8349E rev.1.x had a TSEC FIFO erratum, and I've put an 8360EA chip on an 8360E-MDS board and it came up fine (apart from the PHY timing issues that plagued the 8360), so it would be good to try. > > What interface are you using between the MAC and PHY? I saw somewhat > > similar weirdness at gigabit on a board when using RGMII and the clock > > delays in the PHY and PCB didn't match up correctly (Section 5.12.2 from > > the 88e1111 manual). If you aren't using RGMII, this wouldn't be your > > issue though... > > > > We're using GMII, exactly the same as the Freescale eval board. I did a > very quick test with the board in RGMII mode as well, and the board > behaved in exactly the same way it does in GMII mode. all I can say is git grep R_TSEC for more TSEC frequency & timing knobs... hth, Kim _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
