If an instruction uses a 64 bit register which consists of an even-odd pair
of 32 bit registers and if the register specifier in the instruction is
odd an opd trap is raised.
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 285 +++--
1
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 175 -
1 file changed, 156 insertions(+), 19 deletions(-)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 4423130..b9668a5 100644
--- a/target-tricore
Wrong braces on the restore of the cached TCGv SV and V bit could lead to
a wrong PSW. While at this it removes unnecessary braces for the restore
of the cached TCGv AV and SAV bits.
Signed-off-by: Bastian Koppelmann
---
target-tricore/helper.c | 8
1 file changed, 4 insertions(+), 4
On 12/01/2015 01:16 PM, Amit Shah wrote:
> Ping.
>
> I haven't received any responses so far, please let me know if you're
> planning on doing this.
>
Sorry Amit, no noticeable changes from me.
Cheers,
Bastian
On 12/12/2015 11:36 AM, Paolo Bonzini wrote:
> Cc: Bastian Koppelmann
> Signed-off-by: Paolo Bonzini
> ---
> target-tricore/helper.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
This doesn't look like something which should go into 2.5, so I'll ad
Signed-off-by: Bastian Koppelmann
---
v2 -> v3:
- add raise_exception_sync_helper wrapper to be used by
helper function that generate traps such that
target-tricore/op_helper.c | 33 ++---
1 file changed, 30 insertions(+), 3 deletions(-)
diff --gi
- drop PATCH[2/5]: target-tricore: Save the pc before CSA operations for
exceptions
Bastian Koppelmann (4):
target-tricore: Add trap handling & SOVF/OVF traps
target-tricore: add context managment trap generation
target-tricore: add illegal opcode trap generation
target-tricore: ad
Add the infrastructure needed to generate and handle traps and
implement the generation of SOVF and OVF traps.
Signed-off-by: Bastian Koppelmann
---
v2 -> v3:
- raise_exception_sync_internal now directly modifies PC without
using the do_interrupt hook
- remove do_interrupt h
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 175 -
1 file changed, 156 insertions(+), 19 deletions(-)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index c7a3c77..f0de343
If an instruction uses a 64 bit register which consists of an even-odd pair
of 32 bit registers and if the register specifier in the instruction is
odd an opd trap is raised.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 285
If the cached bits for C, V, SV, AV, or SAV were set, they would
not be saved during the context save since env->PSW was stored instead
of properly reading them using psw_read().
Signed-off-by: Bastian Koppelmann
---
target-tricore/op_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 delet
ementation
--------
Bastian Koppelmann (6):
target-tricore: fix save_context_upper using env->PSW
target-tricore: Fix wrong precedences on psw_write
target-tricore: Add trap handling & SOVF/OVF traps
target-tricore: add
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-Id: <1455889426-1923-3-git-send-email-kbast...@mail.uni-paderborn.de>
---
target-tricore/op_helper.c | 33 ++---
1 file changed, 30 insertions(+), 3 deletions(-)
diff --git a/target-t
Wrong braces on the restore of the cached TCGv SV and V bit could lead to
a wrong PSW. While at this it removes unnecessary braces for the restore
of the cached TCGv AV and SAV bits.
Signed-off-by: Bastian Koppelmann
---
target-tricore/helper.c | 8
1 file changed, 4 insertions(+), 4
If the cached bits for C, V, SV, AV, or SAV were set, they would
not be saved during the context save since env->PSW was stored instead
of properly reading them using psw_read().
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target-tricore/op_helper.c | 2 +-
1 f
Add the infrastructure needed to generate and handle traps and
implement the generation of SOVF and OVF traps.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-Id: <1455889426-1923-2-git-send-email-kbast...@mail.uni-paderborn.de>
---
target-tricore/cpu.h
If an instruction uses a 64 bit register which consists of an even-odd pair
of 32 bit registers and if the register specifier in the instruction is
odd an opd trap is raised.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-Id: <1455889426-1923-5-git-send-email-kb
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Message-Id: <1455889426-1923-4-git-send-email-kbast...@mail.uni-paderborn.de>
---
target-tricore/translate.c | 175 -
1 file changed, 156 insertions(+), 19 deletions(-)
diff -
Hi,
On 02/25/2016 01:24 PM, wangyan (AQ) wrote:
>
>
> Hi all:
> AFAIK, there're several ways to test qemu:
> 1) virt-test, which is driven by autotest or avocado-vt, based on qemu-kvm
> 2) Qtest��using instruction ��make check V=1��, which aims to do low level
> tests, that is to test function
The add.f and sub.f to be implemented don't use 64 bit registers
and a general usage of CHECK_REG_PAIR would always generate an
exception for them.
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --
Signed-off-by: Bastian Koppelmann
---
target-tricore/fpu_helper.c | 30 ++
target-tricore/helper.h | 1 +
target-tricore/translate.c | 3 +++
3 files changed, 34 insertions(+)
diff --git a/target-tricore/fpu_helper.c b/target-tricore/fpu_helper.c
index b840c20
exception.
Cheers,
Bastian
Bastian Koppelmann (7):
target-tricore: Add FPU infrastructure
target-tricore: Move general CHECK_REG_PAIR of decode_rrr_divide
target-tricore: add add.f/sub.f instructions
target-tricore: Add mul.f instruction
target-tricore: Add div.f instruction
target-tricore
Signed-off-by: Bastian Koppelmann
---
target-tricore/fpu_helper.c | 29 +
target-tricore/helper.h | 1 +
target-tricore/translate.c | 3 +++
3 files changed, 33 insertions(+)
diff --git a/target-tricore/fpu_helper.c b/target-tricore/fpu_helper.c
index 70e529c
Signed-off-by: Bastian Koppelmann
---
target-tricore/fpu_helper.c | 46 +
target-tricore/helper.h | 2 ++
target-tricore/translate.c | 6 ++
3 files changed, 54 insertions(+)
diff --git a/target-tricore/fpu_helper.c b/target-tricore
Signed-off-by: Bastian Koppelmann
---
target-tricore/fpu_helper.c | 29 +
target-tricore/helper.h | 1 +
target-tricore/translate.c | 3 +++
3 files changed, 33 insertions(+)
diff --git a/target-tricore/fpu_helper.c b/target-tricore/fpu_helper.c
index ee8b687
Signed-off-by: Bastian Koppelmann
---
target-tricore/fpu_helper.c | 31 +++
target-tricore/helper.h | 2 ++
target-tricore/translate.c | 6 ++
3 files changed, 39 insertions(+)
diff --git a/target-tricore/fpu_helper.c b/target-tricore/fpu_helper.c
index
This patch adds a file for all the FPU related helpers with all the includes,
useful defines, and a function to update the status bits. Additionally it adds
a mask for the rounding mode bits of PSW as well as all the opcodes for the
FPU instructions.
Signed-off-by: Bastian Koppelmann
---
target
Hi,
this series tackles the bugfixes found during FPU implementation
and are mostly on liners. This includes a missing break in a switch
statement, a forgotten reset of an OVF bit, and psw_read() clearing
too many bits.
Cheers,
Bastian
Bastian Koppelmann (3):
target-tricore: add missing break
When this instruction does not produce an overflow the corresponding
bit has to be reset.
Signed-off-by: Bastian Koppelmann
---
target-tricore/op_helper.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target-tricore/op_helper.c b/target-tricore/op_helper.c
index 55f6724..40656c3 100644
psw_read() ought to sync the PSW value with the
cached status bits (C,V,SV,AV,SAV). For this the bits
are cleared in the PSW before they are written from the
cached bits. The clear mask is too big and clears two
additional bits.
Signed-off-by: Bastian Koppelmann
---
target-tricore/helper.c | 2
After decoding/translating a RRR_DIVIDE type instruction we would simply
fall through and would decode/translate another unintended RRR2_MADD
instruction.
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-tricore
On 06/24/2015 02:01 PM, Paolo Bonzini wrote:
Spotted by Coverity, because (env->PCXI & MASK_PCXI_PCPN) >> 24
is always zero. The immediately preceding assignment is also
wrong though.
Signed-off-by: Paolo Bonzini
---
target-tricore/op_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 de
The following changes since commit dc1e1350f8061021df765b396295329797d66933:
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
(2015-06-26 15:57:43 +0100)
are available in the git repository at:
https://github.com/bkoppelmann/qemu-tricore-upstream.git
tags/pull-tric
From: Paolo Bonzini
Spotted by Coverity, because (env->PCXI & MASK_PCXI_PCPN) >> 24
is always zero. The immediately preceding assignment is also
wrong though.
Signed-off-by: Paolo Bonzini
Signed-off-by: Bastian Koppelmann
Message-Id: <1435147270-1040-1-git-send-email-pbo
On 09/14/2015 07:11 PM, Richard Henderson wrote:
On 09/13/2015 01:34 AM, Bastian Koppelmann wrote:
Looking at the article, user mode seems to be optional, so I'm not against it,
but it does look weird. How does ork1sim do it?
It's haphazard. There are checks for supervisor in t
On 09/03/2015 02:17 AM, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
linux-user/main.c | 45
target-openrisc/cpu.c | 1 +
target-openrisc/cpu.h | 9 +
target-openrisc/interrupt.c| 1 +
tar
/fpu_helper.c | 252 +--
target-openrisc/helper.h | 25 +++--
target-openrisc/translate.c | 118 +++-
3 files changed, 129 insertions(+), 266 deletions(-)
Reviewed-by: Bastian Koppelmann
Cheers,
Bastian
On 09/03/2015 02:17 AM, Richard Henderson wrote:
Avoids warnings from unused variables etc.
Signed-off-by: Richard Henderson
---
target-openrisc/translate.c | 20
1 file changed, 4 insertions(+), 16 deletions(-)
Reviewed-by: Bastian Koppelmann
Cheers,
Bastian
On 09/03/2015 02:17 AM, Richard Henderson wrote:
+
+void HELPER(ove)(CPUOpenRISCState *env, target_ulong test)
+{
+if (unlikely(test) && (env->sr & SR_OVE)) {
+OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
+CPUState *cs = CPU(cpu);
+
+cs->exception_index = EXCP_RANGE
wever those are mostly minor issues, so
Reviewed-by: Bastian Koppelmann
Cheers,
Bastian
[1]
https://github.com/openrisc/doc/blob/master/openrisc-arch-1.1-rev0.pdf?raw=true
register */
+target_ulong sr_f;/* the SR_F bit */
A comment that states the expected value of sr_f would be nice.
Other then that,
Reviewed-by: Bastian Koppelmann
On 09/03/2015 02:17 AM, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target-openrisc/translate.c | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
Reviewed-by: Bastian Koppelmann
Cheers,
Bastian
Hi,
Perl 5.22 has deprecated unescaped { inside a regexp, which leads to
very annoying warnings. Since we use checkpatch from the Linux kernel, I
found a corresponding patch [1] that fixes it. Do we just get the new
checkpatch from the kernel, or do we integrate the patch ourself?
[1] https:
On 09/03/2015 02:17 AM, Richard Henderson wrote:
{
/* Sync the tb dependent flag between translate and runtime. */
-if (dc->tb_flags != dc->synced_flags) {
-tcg_gen_movi_tl(env_flags, dc->tb_flags);
+if ((dc->tb_flags ^ dc->synced_flags) & D_FLAG) {
+tcg_gen_mov
e and is clearly for another patch, so
Reviewed-by: Bastian Koppelmann
Cheers,
Bastian
if (cpu->env.sr & SR_OVE) {
-raise_exception(cpu, EXCP_RANGE);
-}
-
-return result;
-}
This ought to be part of patch 02, where you removed the last use of
helper_mul32.
Other than that,
Reviewed-by: Bastian Koppelmann
Cheers,
Bastian
On 09/03/2015 02:17 AM, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target-openrisc/helper.h | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
Reviewed-by: Bastian Koppelmann
(-)
Reviewed-by: Bastian Koppelmann
On 09/04/2015 04:23 PM, Eric Blake wrote:
On 09/04/2015 06:50 AM, Bastian Koppelmann wrote:
Hi,
Perl 5.22 has deprecated unescaped { inside a regexp, which leads to
very annoying warnings. Since we use checkpatch from the Linux kernel, I
found a corresponding patch [1] that fixes it. Do we
passed through in regex; marked by
<-- HERE in m/^\({ <-- HERE / at scripts/checkpatch.pl line 4483.
A fix in kernel can be found here: https://lkml.org/lkml/2015/7/8/1049. Since
we diverged a bit from the kernel, I only fixed the warnings I could find.
Signed-off-by: Bastian Koppelmann
--
+++
3 files changed, 78 insertions(+), 58 deletions(-)
Reviewed-by: Bastian Koppelmann
Cheers,
Bastian
---
1 file changed, 75 insertions(+), 125 deletions(-)
Reviewed-by: Bastian Koppelmann
On 09/03/2015 02:17 AM, Richard Henderson wrote:
-if (dc->mem_idx == MMU_USER_IDX) {
-gen_illegal_exception(dc);
-return;
+{
+TCGv_i32 tmp = tcg_temp_new_i32();
+tcg_gen_trunc_tl_i32(tmp, cpu_R[ra]);
+tcg_gen_ori_i32(tmp,
On 09/03/2015 02:17 AM, Richard Henderson wrote:
Not documented as disabled for user mode.
Signed-off-by: Richard Henderson
---
target-openrisc/translate.c | 32
1 file changed, 32 deletions(-)
Reviewed-by: Bastian Koppelmann
Cheers,
Bastian
On 09/03/2015 02:17 AM, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target-openrisc/translate.c | 106
1 file changed, 106 insertions(+)
Reviewed-by: Bastian Koppelmann
Cheers,
Bastian
ed-by: Bastian Koppelmann
Cheers,
Bastian
On 09/06/2015 10:36 PM, Richard Henderson wrote:
On Sep 5, 2015 14:35, Bastian Koppelmann wrote:
IIRC a lot of the registers are supervisor only, e.g. VR, NPC or SR and
the manual is fairly clear about that. User mode cpu ought not to read
these registers unconditionally.
When I last
Am 15.08.2015 um 16:28 schrieb Peter Crosthwaite:
From: Peter Crosthwaite
The bootloader can just pass EM_TRICORE directly, as that
is architecture specific code.
This removes another architecture specific definition from the global
namespace.
Cc: Bastian Koppelmann
Signed-off-by: Peter
ould like to get some
Acked-by from other maintainers first.
Ok, thanks!
So *ping* to the other CPU core maintainers here ... could I get some
more ACKs, please?
Thomas
Acked-by: Bastian Koppelmann
Add instructions of SSR opcode format.
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 57 ++
1 file changed, 57 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 108619c..7553870 100644
--- a
Add basic board to allow systemmode emulation
Signed-off-by: Bastian Koppelmann
---
hw/tricore/Makefile.objs | 1 +
hw/tricore/tricore_testboard.c | 130 +
include/hw/tricore/tricore.h | 54 +
3 files changed, 185 insertions
Add instructions of SBR opcode format.
Add gen_loop micro-op generator function.
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 69 ++
1 file changed, 69 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore
Add TriCore target stubs, QOM cpu and basic machine.
Signed-off-by: Bastian Koppelmann
---
arch_init.c | 2 +
configure | 13 ++
cpu-exec.c | 11 +-
cpus.c | 6 +
default-configs
Add instructions of SLR, SSRO and SRO opcode format.
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 149 +
1 file changed, 149 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index e98af65
Add basic softmmu support for TriCore
Signed-off-by: Bastian Koppelmann
---
target-tricore/helper.c| 54 +-
target-tricore/op_helper.c | 33 +++-
2 files changed, 85 insertions(+), 2 deletions(-)
diff --git a/target
Add instructions of SB opcode format.
Add helper call/ret.
Add micro-op generator functions for branches.
Add makro to generate helper functions.
Signed-off-by: Bastian Koppelmann
---
target-tricore/helper.h| 5 ++
target-tricore/op_helper.c | 192
Add instructions of SSRS and SLRO opcode format.
Add micro-op generator functions for indirect loads.
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 52 ++
1 file changed, 52 insertions(+)
diff --git a/target-tricore/translate.c b
Add instructions of SRC opcode format.
Add helper for sh arithmetic carry.
Add micro-op generator functions for conditional add/sub/mov and sh.
Signed-off-by: Bastian Koppelmann
---
target-tricore/helper.h| 19 +
target-tricore/op_helper.c | 36 +
target-tricore/translate.c
Add tcg and cpu model initialization.
Add gen_intermediate_code function.
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 160 +++-
target-tricore/translate_init.c | 30
2 files changed, 189 insertions(+), 1 deletion(-)
diff
Add instructions of SC opcode format.
Add makro to generate helper with 1 arg.
Add micro-op generator functions for indirect loads.
Signed-off-by: Bastian Koppelmann
---
target-tricore/helper.h| 2 +-
target-tricore/op_helper.c | 40 +
target-tricore
es of patches. Another one will follow, which adds a lot of the
32 bit long instructions.
Peter Maydall: Sorry if i spammed you with mails. The --cc option of git
confused me a little bit, which resulted in a SMTP 550 error.
All the best
Bastian
Bastian Koppelmann (15):
target-tricore: Add target
Add instructions of SRR opcode format.
Add micro-op generator function for ssov.
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 140 -
1 file changed, 139 insertions(+), 1 deletion(-)
diff --git a/target-tricore/translate.c b
Add instructions of SBC and SBRN opcode format.
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 45 -
1 file changed, 44 insertions(+), 1 deletion(-)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index
Add instructions of SR opcode format.
Add micro-op generator functions for saturate and rsubi.
Add helper return from exception (rfe).
Signed-off-by: Bastian Koppelmann
---
target-tricore/helper.h| 1 +
target-tricore/op_helper.c | 58 ++
target-tricore/translate.c | 144
Hi Peter,
On 07/07/2014 08:24 PM, Peter Maydell wrote:
I think you probably want the configure and default-configs changes to
be at the end of the patch series (or at least part way through it),
not at the start. The general approach is: * some patches which
implement the basic absolute minimu
On 03/01/2016 07:21 PM, Richard Henderson wrote:
> On 03/01/2016 08:24 AM, Bastian Koppelmann wrote:
>> +
>> +lt = float32_lt_quiet(arg1, arg2, &env->fp_status);
>> +eq = float32_eq_quiet(arg1, arg2, &env->fp_status);
>> +uo = float32_unordered
On 03/08/2016 03:42 PM, Richard Henderson wrote:
> On 03/08/2016 05:20 AM, Bastian Koppelmann wrote:
>> On 03/01/2016 07:21 PM, Richard Henderson wrote:
>>> On 03/01/2016 08:24 AM, Bastian Koppelmann wrote:
>>>> +
>>>> +lt = float32_lt_quiet(
On 03/08/2016 03:42 PM, Richard Henderson wrote:
> On 03/08/2016 05:20 AM, Bastian Koppelmann wrote:
>> On 03/01/2016 07:21 PM, Richard Henderson wrote:
>>> On 03/01/2016 08:24 AM, Bastian Koppelmann wrote:
>>>> +
>>>> +lt = float32_lt_quiet(
On 03/08/2016 04:37 PM, Richard Henderson wrote:
> On 03/08/2016 10:11 AM, Bastian Koppelmann wrote:
>> On 03/08/2016 03:42 PM, Richard Henderson wrote:
>>> On 03/08/2016 05:20 AM, Bastian Koppelmann wrote:
>>>> On 03/01/2016 07:21 PM, Richard Henderson wrote:
>>
Signed-off-by: Bastian Koppelmann
---
v1 -> v2:
- Make exceptional case exceptional
target-tricore/fpu_helper.c | 29 +
target-tricore/helper.h | 1 +
target-tricore/translate.c | 3 +++
3 files changed, 33 insertions(+)
diff --git a/target-tric
Signed-off-by: Bastian Koppelmann
---
v1 -> v2:
- Make exceptional case exceptional
target-tricore/fpu_helper.c | 29 +
target-tricore/helper.h | 1 +
target-tricore/translate.c | 3 +++
3 files changed, 33 insertions(+)
diff --git a/target-tric
Signed-off-by: Bastian Koppelmann
---
v1 -> v2:
- Make exceptional case exceptional
- switch arg1 and arg2 in float32_##op() since sub would otherwise
produce false results
- undo inline on f_update_psw_flags() since it is now used
target-tricore/fpu_helper.c |
The add.f and sub.f to be implemented don't use 64 bit registers
and a general usage of CHECK_REG_PAIR would always generate an
exception for them.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 10 --
1 file changed, 8 inser
This patch adds a file for all the FPU related helpers with all the includes,
useful defines, and a function to update the status bits. Additionally it adds
a mask for the rounding mode bits of PSW as well as all the opcodes for the
FPU instructions.
Signed-off-by: Bastian Koppelmann
---
v1
Signed-off-by: Bastian Koppelmann
---
v1 -> v2:
- ftoi/itof now use f_update_psw_flags to update exception flags
target-tricore/fpu_helper.c | 35 +++
target-tricore/helper.h | 2 ++
target-tricore/translate.c | 6 ++
3 files changed, 43 inserti
div
- switch arg1 and arg2 in float32_##op() since sub would otherwise
produce false results
- add TriCore to softfloat-specialize.h
- add fpu_set_state() which sets fpu config on psw_write() and cpu_reset
- add f_get_excp_flags which is used to ignore input_denormal flag
Bast
Signed-off-by: Bastian Koppelmann
---
v1 -> v2:
- fcmp now uses float32_compare_quiet instead of doing it by hand
- fcmp now uses f_update_psw_flags to set excp flags
target-tricore/fpu_helper.c | 23 +++
target-tricore/helper.h | 1 +
target-tric
The add.f and sub.f to be implemented don't use 64 bit registers
and a general usage of CHECK_REG_PAIR would always generate an
exception for them.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 10 --
1 file changed, 8 inser
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
v2 -> v3:
- substitute f_get_excp_flags() with get_float_exception_flags()
- remove float32_squash_input_denormal()
target-tricore/fpu_helper.c | 26 ++
target-tricore/helper.h |
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
v2 -> v3:
- substitute f_get_excp_flags() with get_float_exception_flags()
- remove float32_squash_input_denormal()
target-tricore/fpu_helper.c | 29 -
target-tricore/helper.h |
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
v2 -> v3:
- substitute f_get_excp_flags() with get_float_exception_flags()
- remove float32_squash_input_denormal()
target-tricore/fpu_helper.c | 26 ++
target-tricore/helper.h |
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target-tricore/fpu_helper.c | 23 +++
target-tricore/helper.h | 1 +
target-tricore/translate.c | 3 +++
3 files changed, 27 insertions(+)
diff --git a/target-tricore/fpu_helper.c b/target-tricore
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target-tricore/fpu_helper.c | 34 ++
target-tricore/helper.h | 2 ++
target-tricore/translate.c | 6 ++
3 files changed, 42 insertions(+)
diff --git a/target-tricore/fpu_helper.c b
This patch adds a file for all the FPU related helpers with all the includes,
useful defines, and a function to update the status bits. Additionally it adds
a mask for the rounding mode bits of PSW as well as all the opcodes for the
FPU instructions.
Signed-off-by: Bastian Koppelmann
---
v2
- add f_get_excp_flags which is used to ignore input_denormal flag
Bastian Koppelmann (7):
target-tricore: Add FPU infrastructure
target-tricore: Move general CHECK_REG_PAIR of decode_rrr_divide
target-tricore: add add.f/sub.f instructions
target-tricore: Add mul.f instruction
target-tricore: Add
On 03/09/2016 04:59 PM, Richard Henderson wrote:
> On 03/09/2016 05:42 AM, Bastian Koppelmann wrote:
>> This patch adds a file for all the FPU related helpers with all the
>> includes,
>> useful defines, and a function to update the status bits. Additionally
>> it adds
to ignore input_denormal flag
Bastian Koppelmann (7):
target-tricore: Add FPU infrastructure
target-tricore: Move general CHECK_REG_PAIR of decode_rrr_divide
target-tricore: add add.f/sub.f instructions
target-tricore: Add mul.f instruction
target-tricore: Add div.f instruction
target-tri
The add.f and sub.f to be implemented don't use 64 bit registers
and a general usage of CHECK_REG_PAIR would always generate an
exception for them.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 10 --
1 file changed, 8 inser
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
v3 -> v4:
- use f_get_excp_flags() again
target-tricore/fpu_helper.c | 26 ++
target-tricore/helper.h | 1 +
target-tricore/translate.c | 3 +++
3 files changed, 30 insertions(+)
d
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
v3 -> v4:
- use f_get_excp_flags() again
target-tricore/fpu_helper.c | 29 -
target-tricore/helper.h | 2 ++
target-tricore/translate.c | 6 ++
3 files changed, 36 insertions(+)
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