Signed-off-by: Bastian Koppelmann <kbast...@mail.uni-paderborn.de>
---
v1 -> v2:
- Make exceptional case exceptional
- switch arg1 and arg2 in float32_##op() since sub would otherwise
produce false results
- undo inline on f_update_psw_flags() since it is now used
target-tricore/fpu_helper.c | 32 +++++++++++++++++++++++++++++++-
target-tricore/helper.h | 2 ++
target-tricore/translate.c | 6 ++++++
3 files changed, 39 insertions(+), 1 deletion(-)
diff --git a/target-tricore/fpu_helper.c b/target-tricore/fpu_helper.c
index 07a0a1e..f453aae 100644
--- a/target-tricore/fpu_helper.c
+++ b/target-tricore/fpu_helper.c
@@ -51,7 +51,7 @@ static inline bool f_is_denormal(float32 arg)
return float32_is_zero_or_denormal(arg) && !float32_is_zero(arg);
}
-static inline void f_update_psw_flags(CPUTriCoreState *env, uint8_t flags)
+static void f_update_psw_flags(CPUTriCoreState *env, uint8_t flags)
{
set_float_exception_flags(0, &env->fp_status);
@@ -78,3 +78,33 @@ static inline void f_update_psw_flags(CPUTriCoreState *env,
uint8_t flags)
flags */
env->FPU_FS = 1;
}
+
+#define FADD_SUB(op)
\
+uint32_t helper_f##op(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
\
+{
\
+ float32 arg1 = make_float32(r1);
\
+ float32 arg2 = make_float32(r2);
\
+ uint32_t flags;
\
+ float32 f_result;
\
+
\
+ arg1 = float32_squash_input_denormal(arg1, &env->fp_status);
\
+ arg2 = float32_squash_input_denormal(arg2, &env->fp_status);
\
+
\
+ f_result = float32_##op(arg2, arg1, &env->fp_status);
\
+ flags = f_get_excp_flags(env);
\
+ if (flags) {
\
+ /* If the output is a NaN, but the inputs aren't,
\
+ we return a unique value. */
\
+ if ((flags & float_flag_invalid)
\
+ && !float32_is_any_nan(arg1)
\
+ && !float32_is_any_nan(arg2)) {
\
+ f_result = ADD_NAN;
\
+ }
\
+ f_update_psw_flags(env, flags);
\
+ } else {
\
+ env->FPU_FS = 0;
\
+ }
\
+ return (uint32_t)f_result;
\
+}
+FADD_SUB(add)
+FADD_SUB(sub)
diff --git a/target-tricore/helper.h b/target-tricore/helper.h
index 2c8ed78..2f4a2bb 100644
--- a/target-tricore/helper.h
+++ b/target-tricore/helper.h
@@ -105,6 +105,8 @@ DEF_HELPER_FLAGS_1(parity, TCG_CALL_NO_RWG_SE, i32, i32)
/* float */
DEF_HELPER_FLAGS_4(pack, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32, i32)
DEF_HELPER_1(unpack, i64, i32)
+DEF_HELPER_3(fadd, i32, env, i32, i32)
+DEF_HELPER_3(fsub, i32, env, i32, i32)
/* dvinit */
DEF_HELPER_3(dvinit_b_13, i64, env, i32, i32)
DEF_HELPER_3(dvinit_b_131, i64, env, i32, i32)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 469f721..3f54987 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -7061,6 +7061,12 @@ static void decode_rrr_divide(CPUTriCoreState *env,
DisasContext *ctx)
gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
break;
+ case OPC2_32_RRR_ADD_F:
+ gen_helper_fadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);
+ break;
+ case OPC2_32_RRR_SUB_F:
+ gen_helper_fsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);
+ break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
--
2.7.2
