Add tcg and cpu model initialization.
Add gen_intermediate_code function.
Signed-off-by: Bastian Koppelmann <kbast...@mail.uni-paderborn.de>
---
target-tricore/translate.c | 160 +++++++++++++++++++++++++++++++++++++++-
target-tricore/translate_init.c | 30 ++++++++
2 files changed, 189 insertions(+), 1 deletion(-)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index f92f654..2b23afa 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -26,6 +26,18 @@
#include "exec/helper-proto.h"
#include "exec/helper-gen.h"
+/*
+ * TCG registers
+ */
+static TCGv cpu_PC;
+static TCGv cpu_PCXI;
+static TCGv cpu_PSW;
+static TCGv cpu_ICR;
+/* GPR registers */
+static TCGv cpu_gpr_a[16];
+static TCGv cpu_gpr_d[16];
+static TCGv_ptr cpu_env;
+#include "exec/gen-icount.h"
static const char *regnames_a[] = {
"a0" , "a1" , "a2" , "a3" , "a4" , "a5" ,
@@ -39,6 +51,25 @@ static const char *regnames_d[] = {
"d12" , "d13" , "d14" , "d15",
};
+typedef struct DisasContext {
+ struct TranslationBlock *tb;
+ target_ulong pc, saved_pc;
+ uint32_t opcode;
+ int singlestep_enabled;
+ /* Routine used to access memory */
+ int mem_idx;
+ uint32_t hflags, saved_hflags;
+ int bstate;
+} DisasContext;
+
+enum {
+
+ BS_NONE = 0,
+ BS_STOP = 1,
+ BS_BRANCH = 2,
+ BS_EXCP = 3,
+};
+
void tricore_cpu_dump_state(CPUState *cs, FILE *f,
fprintf_function cpu_fprintf, int flags)
{
@@ -64,10 +95,92 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f,
}
+static int insn_bytes;
+
+static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
+{
+}
+
+static void decode_32Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
+{
+}
+
+static void decode_opc(CPUTRICOREState *env, DisasContext *ctx, int *is_branch)
+{
+ /* 16-Bit Instruction */
+ if ((ctx->opcode & 0x1) == 0) {
+ insn_bytes = 2;
+ decode_16Bit_opc(env, ctx);
+ /* 32-Bit Instruction */
+ } else {
+ insn_bytes = 4;
+ decode_32Bit_opc(env, ctx);
+ }
+}
+
static inline void
gen_intermediate_code_internal(TRICORECPU *cpu, struct TranslationBlock *tb,
int search_pc)
{
+ CPUState *cs = CPU(cpu);
+ CPUTRICOREState *env = &cpu->env;
+ DisasContext ctx;
+ target_ulong pc_start;
+ int num_insns;
+ uint16_t *gen_opc_end;
+
+ if (search_pc) {
+ qemu_log("search pc %d\n", search_pc);
+ }
+
+ num_insns = 0;
+ insn_bytes = 4;
+
+ pc_start = tb->pc;
+ gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
+ ctx.pc = pc_start;
+ ctx.saved_pc = -1;
+ ctx.tb = tb;
+ ctx.singlestep_enabled = cs->singlestep_enabled;
+ ctx.bstate = BS_NONE;
+ ctx.mem_idx = cpu_mmu_index(env);
+
+ tcg_clear_temp_count();
+ gen_tb_start();
+ while (ctx.bstate == BS_NONE) {
+ ctx.opcode = cpu_ldl_code(env, ctx.pc);
+ decode_opc(env, &ctx, 0);
+
+ num_insns++;
+
+ ctx.pc += insn_bytes;
+ if (tcg_ctx.gen_opc_ptr >= gen_opc_end) {
+ break;
+ }
+ if (singlestep) {
+ break;
+ }
+ }
+
+ gen_tb_end(tb, num_insns);
+ *tcg_ctx.gen_opc_ptr = INDEX_op_end;
+ if (search_pc) {
+ printf("done_generating search pc\n");
+ } else {
+ tb->size = ctx.pc - pc_start;
+ tb->icount = num_insns;
+ }
+ if (tcg_check_temp_count()) {
+ printf("LEAK at %08x\n", env->active_tc.PC);
+ }
+
+#ifdef DEBUG_DISAS
+ if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
+ qemu_log("IN: %s\n", lookup_symbol(pc_start));
+ log_target_disas(env, pc_start, ctx.pc - pc_start, 0);
+ qemu_log("\n");
+ }
+#endif
}
void
@@ -96,13 +209,58 @@ restore_state_to_opc(CPUTRICOREState *env,
TranslationBlock *tb, int pc_pos)
void cpu_state_reset(CPUTRICOREState *env)
{
+ /* Reset Regs to Default Value */
+ env->active_tc.PSW = 0xb80;
+}
+
+static void tricore_tcg_init_csfr(void)
+{
+ cpu_PCXI = tcg_global_mem_new(TCG_AREG0,
+ offsetof(CPUTRICOREState, active_tc.PCXI), "PCXI");
+ cpu_PSW = tcg_global_mem_new(TCG_AREG0,
+ offsetof(CPUTRICOREState, active_tc.PSW), "PSW");
+ cpu_PC = tcg_global_mem_new(TCG_AREG0,
+ offsetof(CPUTRICOREState, active_tc.PC), "PC");
+ cpu_ICR = tcg_global_mem_new(TCG_AREG0,
+ offsetof(CPUTRICOREState, active_tc.ICR), "ICR");
}
void tricore_tcg_init(void)
{
+ int i;
+ static int inited;
+ if (inited) {
+ return;
+ }
+ cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ /* reg init */
+ for (i = 0 ; i < 16 ; i++) {
+ cpu_gpr_a[i] = tcg_global_mem_new(TCG_AREG0,
+ offsetof(CPUTRICOREState,
active_tc.gpr_a[i]),
+ regnames_a[i]);
+ }
+ for (i = 0 ; i < 16 ; i++) {
+ cpu_gpr_d[i] = tcg_global_mem_new(TCG_AREG0,
+ offsetof(CPUTRICOREState,
active_tc.gpr_d[i]),
+ regnames_d[i]);
+ }
+ tricore_tcg_init_csfr();
}
TRICORECPU *cpu_tricore_init(const char *cpu_model)
{
- return NULL;
+ TRICORECPU *cpu;
+ CPUTRICOREState *env;
+ const tricore_def_t *def;
+
+ def = cpu_tricore_find_by_name(cpu_model);
+ if (!def) {
+ return NULL;
+ }
+ cpu = TRICORE_CPU(object_new(TYPE_TRICORE_CPU));
+ env = &cpu->env;
+ env->cpu_model = def;
+
+ object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
+ return cpu;
}
diff --git a/target-tricore/translate_init.c b/target-tricore/translate_init.c
index d37d2ba..9eee7dd 100644
--- a/target-tricore/translate_init.c
+++ b/target-tricore/translate_init.c
@@ -16,6 +16,36 @@
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
+struct tricore_def_t {
+ const char *name;
+};
+
+
+static const tricore_def_t tricore_defs[] = {
+ {
+ .name = "TC1796",
+ },
+
+};
+
+static const tricore_def_t *cpu_tricore_find_by_name(const char *name)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(tricore_defs); i++) {
+ if (strcasecmp(name, tricore_defs[i].name) == 0) {
+ return &tricore_defs[i];
+ }
+ }
+ return NULL;
+}
+
void tricore_cpu_list(FILE *f, fprintf_function cpu_fprintf)
{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(tricore_defs); i++) {
+ (*cpu_fprintf)(f, "TRICORE '%s'\n",
+ tricore_defs[i].name);
+ }
}
--
2.0.1
