Add instructions of SLR, SSRO and SRO opcode format.
Signed-off-by: Bastian Koppelmann <kbast...@mail.uni-paderborn.de>
---
target-tricore/translate.c | 149 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 149 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index e98af65..628bd8b 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -783,6 +783,155 @@ static void decode_16Bit_opc(CPUTRICOREState *env,
DisasContext *ctx)
const16 = MASK_OP_SC_CONST8(ctx->opcode);
tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16);
break;
+/* SLR-format */
+ case OPC1_16_SLR_LD_A:
+ r1 = MASK_OP_SLR_D(ctx->opcode);
+ r2 = MASK_OP_SLR_S2(ctx->opcode);
+ tcg_gen_qemu_ld32s(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx);
+ break;
+ case OPC1_16_SLR_LD_A_POSTINC:
+ r1 = MASK_OP_SLR_D(ctx->opcode);
+ r2 = MASK_OP_SLR_S2(ctx->opcode);
+ tcg_gen_qemu_ld32s(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx);
+ tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
+ break;
+ case OPC1_16_SLR_LD_BU:
+ r1 = MASK_OP_SLR_D(ctx->opcode);
+ r2 = MASK_OP_SLR_S2(ctx->opcode);
+ tcg_gen_qemu_ld8u(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx);
+ break;
+ case OPC1_16_SLR_LD_BU_POSTINC:
+ r1 = MASK_OP_SLR_D(ctx->opcode);
+ r2 = MASK_OP_SLR_S2(ctx->opcode);
+ tcg_gen_qemu_ld8u(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx);
+ tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
+ break;
+ case OPC1_16_SLR_LD_H:
+ r1 = MASK_OP_SLR_D(ctx->opcode);
+ r2 = MASK_OP_SLR_S2(ctx->opcode);
+ tcg_gen_qemu_ld16s(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx);
+ break;
+ case OPC1_16_SLR_LD_H_POSTINC:
+ r1 = MASK_OP_SLR_D(ctx->opcode);
+ r2 = MASK_OP_SLR_S2(ctx->opcode);
+ tcg_gen_qemu_ld16s(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx);
+ tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
+ break;
+ case OPC1_16_SLR_LD_W:
+ r1 = MASK_OP_SLR_D(ctx->opcode);
+ r2 = MASK_OP_SLR_S2(ctx->opcode);
+ tcg_gen_qemu_ld32s(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx);
+ break;
+ case OPC1_16_SLR_LD_W_POSTINC:
+ r1 = MASK_OP_SLR_D(ctx->opcode);
+ r2 = MASK_OP_SLR_S2(ctx->opcode);
+ tcg_gen_qemu_ld32s(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx);
+ tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
+ break;
+/* SRO-format */
+ case OPC1_16_SRO_LD_A:
+ address = MASK_OP_SRO_OFF4(ctx->opcode);
+ r2 = MASK_OP_SRO_S2(ctx->opcode);
+ gen_indirect_ld32s(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4);
+ break;
+ case OPC1_16_SRO_LD_BU:
+ r1 = MASK_OP_SRO_S2(ctx->opcode);
+ const16 = MASK_OP_SRO_OFF4(ctx->opcode);
+ gen_indirect_ld8u(ctx, cpu_gpr_d[15], cpu_gpr_a[r1], const16);
+ break;
+ case OPC1_16_SRO_LD_H:
+ r1 = MASK_OP_SRO_S2(ctx->opcode);
+ const16 = MASK_OP_SRO_OFF4(ctx->opcode);
+ gen_indirect_ld16s(ctx, cpu_gpr_d[15], cpu_gpr_a[r1], const16);
+ break;
+ case OPC1_16_SRO_LD_W:
+ address = MASK_OP_SRO_OFF4(ctx->opcode);
+ r2 = MASK_OP_SRO_S2(ctx->opcode);
+ temp = tcg_temp_new();
+ tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address * 4);
+ tcg_gen_qemu_ld32u(cpu_gpr_d[15], temp, ctx->mem_idx);
+ tcg_temp_free(temp);
+ break;
+ case OPC1_16_SRO_ST_A:
+ const16 = MASK_OP_SRO_OFF4(ctx->opcode);
+ r1 = MASK_OP_SRO_S2(ctx->opcode);
+ gen_indirect_st32(ctx, cpu_gpr_a[15], cpu_gpr_a[r1], const16 * 4);
+ break;
+ case OPC1_16_SRO_ST_B:
+ r1 = MASK_OP_SRO_S2(ctx->opcode);
+ const16 = MASK_OP_SRO_OFF4(ctx->opcode);
+ temp = tcg_temp_new();
+ tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0xff);
+ gen_indirect_st8(ctx, temp, cpu_gpr_a[r1], const16);
+ tcg_temp_free(temp);
+ break;
+ case OPC1_16_SRO_ST_H:
+ r1 = MASK_OP_SRO_S2(ctx->opcode);
+ const16 = MASK_OP_SRO_OFF4(ctx->opcode);
+ temp = tcg_temp_new();
+ tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0xffff);
+ gen_indirect_st16(ctx, temp, cpu_gpr_a[r1], const16 * 2);
+ tcg_temp_free(temp);
+ break;
+ case OPC1_16_SRO_ST_W:
+ r1 = MASK_OP_SRO_S2(ctx->opcode);
+ const16 = MASK_OP_SRO_OFF4(ctx->opcode);
+ gen_indirect_st32(ctx, cpu_gpr_d[15], cpu_gpr_a[r1], const16 * 4);
+ break;
+/* SSRO-format */
+ case OPC1_16_SSRO_ST_A:
+ r1 = MASK_OP_SSRO_S1(ctx->opcode);
+ const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
+ gen_indirect_st32(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4);
+ break;
+ case OPC1_16_SSRO_ST_B:
+ r1 = MASK_OP_SSRO_S1(ctx->opcode);
+ const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
+ temp = tcg_temp_new();
+ tcg_gen_andi_tl(temp, cpu_gpr_d[r1], 0xff);
+ gen_indirect_st8(ctx, temp, cpu_gpr_a[15], const16);
+ tcg_temp_free(temp);
+ break;
+ case OPC1_16_SSRO_ST_H:
+ r1 = MASK_OP_SSRO_S1(ctx->opcode);
+ const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
+ temp = tcg_temp_new();
+ tcg_gen_andi_tl(temp, cpu_gpr_d[r1], 0xffff);
+ gen_indirect_st16(ctx, temp, cpu_gpr_a[15], const16 * 2);
+ tcg_temp_free(temp);
+ break;
+ case OPC1_16_SSRO_ST_W:
+ r1 = MASK_OP_SSRO_S1(ctx->opcode);
+ const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
+ gen_indirect_st32(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4);
+ break;
+/* SSRO-format */
+ case OPC1_16_SSRO_ST_A:
+ r1 = MASK_OP_SSRO_S1(ctx->opcode);
+ const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
+ gen_indirect_st32(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4);
+ break;
+ case OPC1_16_SSRO_ST_B:
+ r1 = MASK_OP_SSRO_S1(ctx->opcode);
+ const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
+ temp = tcg_temp_new();
+ tcg_gen_andi_tl(temp, cpu_gpr_d[r1], 0xff);
+ gen_indirect_st8(ctx, temp, cpu_gpr_a[15], const16);
+ tcg_temp_free(temp);
+ break;
+ case OPC1_16_SSRO_ST_H:
+ r1 = MASK_OP_SSRO_S1(ctx->opcode);
+ const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
+ temp = tcg_temp_new();
+ tcg_gen_andi_tl(temp, cpu_gpr_d[r1], 0xffff);
+ gen_indirect_st16(ctx, temp, cpu_gpr_a[15], const16 * 2);
+ tcg_temp_free(temp);
+ break;
+ case OPC1_16_SSRO_ST_W:
+ r1 = MASK_OP_SSRO_S1(ctx->opcode);
+ const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
+ gen_indirect_st32(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4);
+ break;
}
}
--
2.0.1
