On Thu, Jun 05, 2025 at 11:42:22PM +, anisa.su...@gmail.com wrote:
> From: Anisa Su
>
> FM DCD Management command 0x5604 implemented per CXL r3.2 Spec Section
> 7.6.7.6.5
>
> Signed-off-by: Anisa Su
See below...
> ---
> hw/cxl/cxl-mailbox-utils.c | 152 +
Register an event notifier handler to process AP configuration
change events by queuing the event and generating a CRW to let
the guest know its AP configuration has changed
Signed-off-by: Rorie Reyes
Reviewed-by: Anthony Krowiak
---
hw/vfio/ap.c | 31 +++
1 file cha
Changelog:
v12:
- adding locks to 'ap_chsc_sei_nt0_have_event' and 'ap_chsc_sei_nt0_get_event'
v11:
- reverted return type to int for 'ap_chsc_sei_nt0_get_event'
- files reflected are 'ap.c', 'ap-bridge'h, and 'ap-stub.c'
- using defined variables to represent return 0 and 1 to reflect logical
Peter Xu writes:
> On Fri, Jun 06, 2025 at 12:43:04PM -0300, Fabiano Rosas wrote:
>> Peter Xu writes:
>>
>> > On Mon, Jun 02, 2025 at 10:37:54PM -0300, Fabiano Rosas wrote:
>> >> The QAPI converts an empty list on the block-bitmap-mapping input into
>> >> a NULL BitmapMigrationNodeAliasList. Th
Creates an object indicating that an AP configuration change event
has been received and stores it in a queue. These objects will later
be used to store event information for an AP configuration change
when the CHSC instruction is intercepted.
Signed-off-by: Rorie Reyes
---
hw/vfio/ap.c | 12 +++
Handle interception of the CHSC SEI instruction for requests
indicating the guest's AP configuration has changed.
If configuring --without-default-devices, hw/s390x/ap-stub.c
was created to handle such circumstance. Also added the
following to hw/s390x/meson.build if CONFIG_VFIO_AP is
false, it wi
These functions can be invoked by the function that handles interception
of the CHSC SEI instruction for requests indicating the accessibility of
one or more adjunct processors has changed.
Signed-off-by: Rorie Reyes
---
hw/vfio/ap.c | 43
inc
On Thu, Jun 05, 2025 at 11:42:23PM +, anisa.su...@gmail.com wrote:
> From: Anisa Su
>
> FM DCD Managment command 0x5605 implemented per CXL r3.2 Spec Section
> 7.6.7.6.6
>
> Signed-off-by: Anisa Su
See below ..
> ---
> hw/cxl/cxl-mailbox-utils.c | 62
On Fri, Jun 06, 2025 at 11:43:51AM -0700, Fan Ni wrote:
> On Thu, Jun 05, 2025 at 11:42:23PM +, anisa.su...@gmail.com wrote:
> > From: Anisa Su
> >
> > FM DCD Managment command 0x5605 implemented per CXL r3.2 Spec Section
> > 7.6.7.6.6
> >
> > Signed-off-by: Anisa Su
>
> See below ..
>
>
On Mon, Jun 02, 2025 at 10:38:03PM -0300, Fabiano Rosas wrote:
> Do a cleanup of hmp_info_migrate_parameters() before adding more lines
> into it:
>
> - Make sure every parameter asserts that the has_* field is
> set. qmp_query_migrate_parameters should have set them all.
>
> - Remove the if (p
On Mon, Jun 02, 2025 at 10:38:04PM -0300, Fabiano Rosas wrote:
> Add capabilities to MigrationParameters. This structure will hold all
> migration options. Capabilities will go away in the next patch.
>
> Also add capabilities to MigrationParameter as the enum needs to be
> kept in sync with Migra
Hi,
I recently needed to slow down time within a virtual machine, due to a
timeout being hit because my QEMU binary which was not fast enough (gcov
debug build if you're curious about the use case).
Currently, people tend to use -icount shift=X with low values for that,
as it roughly maps ti
On Tue, May 20, 2025 at 01:30:11PM +0200, Magnus Kulke wrote:
> Write CPU register state to MSHV vCPUs. Various mapping functions to
> prepare the payload for the HV call have been implemented.
>
> Signed-off-by: Magnus Kulke
> ---
[...]
> +
> +static void populate_hv_table_reg(const struct Segme
On Mon, Jun 02, 2025 at 10:38:07PM -0300, Fabiano Rosas wrote:
> The concept of capabilities is being merged into the concept of
> parameters. From now on, the commands that handle capabilities are
> deprecated in favor of the commands that handle parameters.
>
> Affected commands:
>
> - migrate-
On Mon, Jun 02, 2025 at 10:38:06PM -0300, Fabiano Rosas wrote:
> Last patch added capabilities to s->parameters. Now we can replace all
> instances of s->capabilities with s->parameters:
>
> - The -global properties now get set directly in s->parameters.
>
> - Accessors from options.c now read fr
On Wed, May 28, 2025 at 04:30:55PM +0200, Magnus Kulke wrote:
> On Tue, May 20, 2025 at 10:22:27PM +, Wei Liu wrote:
> > On Tue, May 20, 2025 at 01:30:11PM +0200, Magnus Kulke wrote:
> > > +/*
> > > + * TODO: support asserting an interrupt using interrup_bitmap
> > > + * it should b
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.1 for any
user-visible changes.
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On Mon, Jun 02, 2025 at 10:38:08PM -0300, Fabiano Rosas wrote:
> Allow the migrate and migrate_incoming commands to pass the migration
> configuration options all at once, dispensing the use of
> migrate-set-parameters and migrate-set-capabilities.
>
> The motivation of this is to simplify the int
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.1 for any
user-visible changes.
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On 5/6/25 23:23, BALATON Zoltan wrote:
On Thu, 5 Jun 2025, Philippe Mathieu-Daudé wrote:
tpm_emulator_ctrlcmd() is not in hot path.
Use the heap instead of the stack, removing
the g_alloca() call.
Typo in subject L -> :
Oops thanks, I hurt my ring finger and have it now tied with the
middle
Now the ramfb will load the vgabios-ramfb.bin unconditionally, but only
the x86 need the vgabios-ramfb.bin, this can cause that when use the
release package on arm64 it can't find the vgabios-ramfb.bin.
Because only seabios will use the vgabios-ramfb.bin, load the rom logic
is x86-specific. For ot
Hi Daniel,
On 6/5/25 10:40 PM, Daniel P. Berrangé wrote:
On Thu, Jun 05, 2025 at 04:24:07PM +0200, Cédric Le Goater wrote:
On 6/5/25 14:21, Gerd Hoffmann wrote:
Hi,
Now the ramfb will load the vgabios-ramfb.bin unconditionally, but only
the x86 need the vgabios-ramfb.bin, this can cause
On Fri, Jun 06, 2025 at 08:26:37AM +0200, Markus Armbruster wrote:
> Daniel P. Berrangé writes:
>
> > On Thu, Jun 05, 2025 at 12:38:09PM +0100, Peter Maydell wrote:
> >> On Thu, 5 Jun 2025 at 11:52, Markus Armbruster wrote:
> >> > +At times contributors may use or create scripts/tools to generat
Le 05/06/2025 à 16:46, Zhang He a écrit :
i write some bare-metal c code need mq_open/mq_unlink syscall, but
the syscall failed in passed name param check, arg1 in this scenario
is the correct address from user-space, arg1 - 1 not.
i have tested in arm cortex-m55 cpu model, maybe should add condi
According to the RISC-V Privileged Specification (version >1.12),
RV32 supports 16 CSRs (pmpcfg0–pmpcfg15) to configure 64 PMP regions
(pmpaddr0–pmpaddr63).
Signed-off-by: Jay Chang
Reviewed-by: Frank Chang
Reviewed-by: Alistair Francis
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/cp
The first patch extends the number of PMP regions supported up to 64,
following the RISC-V Privileged Specification (version >1.12), where
RV32 can have up to 64 PMP regions configured through 16 CSRs.
The second patch makes the PMP region count configurable via a new
CPU parameter `num-pmp-region
On Fri, Jun 06, 2025 at 06:10:31AM +, Kasireddy, Vivek wrote:
> Hi Daniel,
>
> > Subject: Re: [PATCH v5 2/7] ui/spice: Add an option for users to provide a
> > preferred codec
> >
> > On Wed, May 28, 2025 at 10:11:13PM -0700, Vivek Kasireddy wrote:
> > > Giving users an option to choose a par
Previously, the number of PMP regions was hardcoded to 16 in QEMU.
This patch replaces the fixed value with a new `pmp_regions` field,
allowing platforms to configure the number of PMP regions.
If no specific value is provided, the default number of PMP regions
remains 16 to preserve the existing
From: Thomas Huth
In case the default machine has not been compiled into the QEMU
binary, the cpu_hotplug_props test is currently failing. Add a
set_machine('pc') here to make sure that the tests are correctly
skipped in case the machine is not available.
Signed-off-by: Thomas Huth
---
tests/f
On 6/6/25 10:49, Xiaoyao Li wrote:
On 6/3/2025 10:53 PM, Paolo Bonzini wrote:
On 6/3/25 13:26, Philippe Mathieu-Daudé wrote:
On 3/6/25 05:04, Xiaoyao Li wrote:
On 6/3/2025 1:31 AM, Cédric Le Goater wrote:
Use PRI formats where required and fix pointer cast.
Maybe we can make 32-bit build ex
AspeedGPIOClass's parent is SysBusDeviceClass rather than SysBusDevice.
This isn't catastrophic only because sizeof(SysBusDevice) >
sizeof(SysBusDeviceClass).
Fixes: 4b7f956862dc ("hw/gpio: Add basic Aspeed GPIO model for AST2400 and
AST2500")
Closes: https://lists.gnu.org/archive/html/qemu-devel
RISCVIOMMUPciClass and RISCVIOMMUSysClass are defined with missed
parent class, class_init on them may corrupt their parent class
fields.
It's lucky that parent_realize and parent_phases are not initialized
or used until now, so just remove the definitions. They can be added
back when really neces
On 2025/06/06 1:26, Alex Bennée wrote:
From: Nabih Estefan
../tests/qtest/libqos/igb.c:106:5: runtime error: load of misaligned address
0x562040be8e33 for type 'uint32_t', which requires 4 byte alignment
Instead of straight casting the uint8_t array, we can use ldl_le_p and
lduw_l_p to ass
Parent of VirtIOMEMClass is VirtioDeviceClass rather than VirtIODevice.
This isn't catastrophic only because sizeof(VirtIODevice) >
sizeof(VirtioDeviceClass).
Fixes: 910b25766b33 ("virtio-mem: Paravirtualized memory hot(un)plug")
Signed-off-by: Zhenzhong Duan
Reviewed-by: David Hildenbrand
Revie
Hi,
This fix definition of some classes with wrong parent.
Used below script to get a list, hoping all are addressed.
find "$directory" -type d \( -name "roms" -o -name "build" \) -prune -o -type f
\( -name "*.c" -o -name "*.h" \) -print | while read -r file; do
awk '/^(struct |typedef struc
On a system influenced by ERRATA_772415, IOMMU_HW_INFO_VTD_ERRATA_772415_SPR17
is repored by IOMMU_DEVICE_GET_HW_INFO. Due to this errata, even the readonly
range mapped on stage-2 page table could still be written.
Reference from 4th Gen Intel Xeon Processor Scalable Family Specification
Update,
From: Yi Liu
When either 'Set Root Table Pointer' or 'Translation Enable' bit is changed,
the pasid bindings on host side become stale and need to be updated.
Introduce a helper function vtd_refresh_pasid_bind() for that purpose.
Signed-off-by: Yi Liu
Signed-off-by: Zhenzhong Duan
---
hw/i38
VFIO utilizes replay to setup initial shadow iommu mappings.
But when stage-1 page table is configured, it is passed to
host to construct nested page table, there is no replay needed.
Signed-off-by: Zhenzhong Duan
---
hw/i386/intel_iommu.c | 8
1 file changed, 8 insertions(+)
diff --gi
In early days vtd_ce_get_rid2pasid_entry() was used to get pasid entry
of rid2pasid, then it was extended to get any pasid entry. So a new name
vtd_ce_get_pasid_entry is better to match what it actually does.
No functional change intended.
Signed-off-by: Zhenzhong Duan
Reviewed-by: Clément Mathi
When vIOMMU is configured x-flts=on in scalable mode, stage-1 page table
is passed to host to construct nested page table. We need to check
compatibility of some critical IOMMU capabilities between vIOMMU and
host IOMMU to ensure guest stage-1 page table could be used by host.
For instance, vIOMMU
When guest modifies a PASID entry, QEMU will capture the guest pasid selective
pasid cache invalidation, allocate or remove a VTDAddressSpace instance per the
invalidation reasons:
a) a present pasid entry moved to non-present
b) a present pasid entry to be a present entry
c) a non-pre
From: Yi Liu
This traps the guest PASID-based iotlb invalidation request and propagate it
to host.
Intel VT-d 3.0 supports nested translation in PASID granular. Guest SVA support
could be implemented by configuring nested translation on specific PASID. This
is also known as dual stage DMA transl
Now that all infrastructures of supporting passthrough device running
with stage-1 translation are there, enable it now.
Signed-off-by: Zhenzhong Duan
---
hw/i386/intel_iommu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 165998896c..1df
There are many call sites referencing context entry by calling
vtd_dev_to_context_entry() which will traverse the DMAR table.
In most cases we can use cached context entry in vtd_as->context_cache_entry
except when its entry is stale. Currently only global and domain context
invalidation stale it.
FORCE_RESET is different from GLOBAL_INV which updates pasid cache if
underlying pasid entry is still valid, it drops all the pasid caches.
FORCE_RESET isn't a VTD spec defined invalidation type for pasid cache,
only used internally in system level reset.
Signed-off-by: Zhenzhong Duan
---
hw/i3
From: Yi Liu
This replays guest pasid attachments after context cache invalidation.
This is a behavior to ensure safety. Actually, programmer should issue
pasid cache invalidation with proper granularity after issuing a context
cache invalidation.
Signed-off-by: Yi Liu
Signed-off-by: Yi Sun
Si
We already have vtd_find_add_as() to find an AS from BDF+pasid, but this
pasid is passed from PCI subsystem. PCI device supports two request types,
Requests-without-PASID and Requests-with-PASID. Requests-without-PASID
doesn't include a PASID TLP prefix, IOMMU fetches rid_pasid from context
entry a
On Wed, Jun 04, 2025 at 05:56:30PM -0400, Zhuoying Cai wrote:
> Add helper functions for x509 certificate which will be used in the next
> patch for the certificate store.
>
> Signed-off-by: Zhuoying Cai
> ---
> crypto/meson.build | 5 +-
> crypto/x509-utils.c | 166 ++
This adds an new entry VTDPASIDCacheEntry in VTDAddressSpace to cache the
pasid entry and track PASID usage and future PASID tagged DMA address
translation support in vIOMMU.
VTDAddressSpace of PCI_NO_PASID is allocated when device is plugged and
never freed. For other pasid, VTDAddressSpace insta
This captures the guest PASID table entry modifications and
propagates the changes to host to attach a hwpt with type determined
per guest PGTT configuration.
When PGTT is Pass-through(100b), the hwpt on host side is a stage-2
page table(GPA->HPA). When PGTT is First-stage Translation only(001b),
Hi,
After VFIO/IOMMUFD prerequisite patchset got accepted, now this focuses on
stage-1 translation for passthrough device in intel_iommu. I thought it's
time to bump to v1 from rfcv3.
rfcv3 cover-letter:
Per Jason Wang's suggestion, iommufd nesting series[1] is split into
"Enable stage-1 transla
Akihiko Odaki writes:
> On 2025/06/05 20:57, Alex Bennée wrote:
>> Akihiko Odaki writes:
>>
>>> On 2025/06/03 20:01, Alex Bennée wrote:
QOM objects can be embedded in other QOM objects and managed as part
of their lifetime but this isn't the case for
virtio_gpu_virgl_hostmem_regi
* Babu Moger (babu.mo...@amd.com) wrote:
> Add CPUID bit indicates that a WRMSR to MSR_FS_BASE, MSR_GS_BASE, or
> MSR_KERNEL_GS_BASE is non-serializing amd PREFETCHI that the indicates
> support for IC prefetch.
>
> CPUID_Fn8021_EAX
> BitFeature description
> 20 Indicates support for I
If the enum includes values such as "Ok", "Err", or "Error", the TryInto
macro can cause errors. Be careful and qualify identifiers with the full
path, or in the case of TryFrom<>::Error do not use the associated type
at all.
Signed-off-by: Paolo Bonzini
---
rust/qemu-api-macros/src/lib.rs | 7
From: Akihiko Odaki
Windows supports futex-like APIs since Windows 8 and Windows Server
2012.
Signed-off-by: Akihiko Odaki
Link: https://lore.kernel.org/r/20250529-event-v5-2-53b285203...@daynix.com
Signed-off-by: Paolo Bonzini
---
meson.build | 7
include/qemu/fut
This is a standard replacement for Box which is more efficient (it
only
occcupies one word) and provides a backtrace of the error. This could be
plumbed
into &error_abort in the future.
Reviewed-by: Zhao Liu
Signed-off-by: Paolo Bonzini
---
rust/meson.build | 2
The function name is not available in Rust, so make it optional.
Reviewed-by: Zhao Liu
Signed-off-by: Paolo Bonzini
---
include/qapi/error-internal.h | 2 ++
util/error.c | 9 +++--
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/include/qapi/error-internal.h
From: Akihiko Odaki
Use the futex-based implementation of QemuEvent on Windows to
remove code duplication and remove the overhead of event object
construction and destruction.
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
Link: https://lore.kernel.org/r/20250526-event-v4-6-5
No functional change intended.
Suggested-by: Zhao Liu
Reviewed-by: Zhao Liu
Signed-off-by: Paolo Bonzini
---
hw/timer/hpet.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/timer/hpet.c b/hw/timer/hpet.c
index 0fd1337a156..9db027cf76f 100644
--- a/hw/timer/hpet.c
+
From: Akihiko Odaki
qemu-thread used to abstract pthread primitives into futex for the
QemuEvent implementation of POSIX systems other than Linux. However,
this abstraction has one key difference: unlike futex, pthread
primitives require an explicit destruction, and it must be ordered after
wait
Do not silently adjust num_timers, and fail if intcap is 0.
Reviewed-by: Markus Armbruster
Reviewed-by: Zhao Liu
Signed-off-by: Paolo Bonzini
---
hw/timer/hpet.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/hw/timer/hpet.c b/hw/timer/hpet.c
index 9db027cf
From: Zhao Liu
Now that the num_timers field is initialized as a property, someone may
change its default value using qdev_prop_set_uint8(), but the value is
fixed after the Rust code sees it first. Since there is no need to modify
it after realize(), it is not to be necessary to have a BqlCell
This is used to preserve the file and line in a roundtrip from
C Error to Rust and back to C.
Signed-off-by: Paolo Bonzini
---
include/qapi/error-internal.h | 26 ++
rust/wrapper.h| 1 +
util/error.c | 10 +-
3 files changed, 28 i
Provide an implementation of std::error::Error that bridges the Rust
anyhow::Error and std::panic::Location types with QEMU's Error*.
It also has several utility methods, analogous to error_propagate(),
that convert a Result into a return value + Error** pair. One important
difference is that the
The following changes since commit f8a113701dd2d28f3bedb216e59125ddcb77fd05:
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
(2025-06-04 11:43:31 -0400)
are available in the Git repository at:
https://gitlab.com/bonzini/qemu.git tags/for-upstream
for you to fetch c
Reviewed-by: Zhao Liu
Signed-off-by: Paolo Bonzini
---
rust/hw/char/pl011/src/device.rs | 5 +++--
rust/hw/timer/hpet/src/device.rs | 5 +++--
rust/qemu-api/src/qdev.rs| 12
3 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/rust/hw/char/pl011/src/device.rs b/
Remove the need to convert after every read of the BqlCell. Because the
vmstate uses a u8 as the size of the VARRAY, this requires switching
the VARRAY to use num_timers_save; which in turn requires ensuring that
the num_timers_save is always there. For simplicity do this by
removing support for
From: Tom Lendacky
A page state change is typically followed by an access of the page(s) and
results in another VMEXIT in order to map the page into the nested page
table. Depending on the size of page state change request, this can
generate a number of additional VMEXITs. For example, under SNP,
From: Akihiko Odaki
scripts/checkpatch.pl warns for __linux__ saying "architecture specific
defines should be avoided".
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
Link: https://lore.kernel.org/r/20250526-event-v4-4-5b784cc8e...@daynix.com
Signed-off-by: Paolo Bonzini
---
Rust makes the current file available as a statically-allocated string,
but without a NUL terminator. Allow this by storing an optional maximum
length in the Error.
Reviewed-by: Zhao Liu
Signed-off-by: Paolo Bonzini
---
include/qapi/error-internal.h | 9 -
util/error.c
error is new; offset_of is gone.
Reviewed-by: Zhao Liu
Signed-off-by: Paolo Bonzini
---
docs/devel/rust.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/devel/rust.rst b/docs/devel/rust.rst
index d60d56d0a69..47e9677fcb0 100644
--- a/docs/devel/rust.rst
+++ b/docs/de
From: Akihiko Odaki
colo_exit_sem and colo_incoming_sem represent one-shot events so they
can be converted into QemuEvent, which is more lightweight.
Signed-off-by: Akihiko Odaki
Reviewed-by: Fabiano Rosas
Reviewed-by: Philippe Mathieu-Daudé
Link: https://lore.kernel.org/r/20250529-event-v5-8
From: Akihiko Odaki
Document QemuEvent to help choose an appropriate synchronization
primitive.
Signed-off-by: Akihiko Odaki
Link: https://lore.kernel.org/r/20250529-event-v5-12-53b285203...@daynix.com
Signed-off-by: Paolo Bonzini
---
include/qemu/thread.h | 10 ++
1 file changed, 10
From: Peter Maydell
The softfloat get_float_exception_flags() function returns 'int', but
in various places in target/i386 we incorrectly store the returned
value into a uint8_t. This currently has no ill effects because i386
doesn't care about any of the float_flag enum values above 0x40.
Howev
From: Akihiko Odaki
pause_event can utilize qemu_event_reset() to discard events.
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
Link: https://lore.kernel.org/r/20250529-event-v5-7-53b285203...@daynix.com
Signed-off-by: Paolo Bonzini
---
migration/migration.h | 2 +-
migra
From: Peter Maydell
The Intel SDM section 10.2.3.3 on the MXCSR.FTZ bit says that we
flush outputs to zero when we detect underflow, which is after
rounding. Set the detect_ftz flag accordingly.
This allows us to enable the test in fma.c which checks this
behaviour.
Signed-off-by: Peter Maydel
From: Peter Maydell
The x86 DE bit in the FPU and MXCSR status is supposed to be set
when an input denormal is consumed. We didn't previously report
this from softfloat, so the x86 code either simply didn't set
the DE bit or else incorrectly wired it up to denormal_flushed,
depending on which reg
Match the code in hpet.c; this also allows removing the
BqlCell from the num_timers field.
Reviewed-by: Zhao Liu
Signed-off-by: Paolo Bonzini
---
rust/hw/timer/hpet/src/device.rs | 16 +++-
rust/hw/timer/hpet/src/fw_cfg.rs | 7 +++
2 files changed, 10 insertions(+), 13 deletion
Signed-off-by: Paolo Bonzini
---
rust/qemu-api/src/error.rs | 104 +
1 file changed, 104 insertions(+)
diff --git a/rust/qemu-api/src/error.rs b/rust/qemu-api/src/error.rs
index 80157f6ea1b..e114fc4178b 100644
--- a/rust/qemu-api/src/error.rs
+++ b/rust/qemu-a
This is a cleaned up and separated version of the patches at
https://lore.kernel.org/all/20240701145853.1394967-4-pbonz...@redhat.com/
https://lore.kernel.org/all/20240701145853.1394967-5-pbonz...@redhat.com/
Its first user will be the Error bindings; for example a QEMU Error ** can be
converted t
From: Akihiko Odaki
thread_sync_sem is an one-shot event so it can be converted into
QemuEvent, which is more lightweight.
Signed-off-by: Akihiko Odaki
Reviewed-by: Fabiano Rosas
Link: https://lore.kernel.org/r/20250529-event-v5-9-53b285203...@daynix.com
Signed-off-by: Paolo Bonzini
---
migr
From: Akihiko Odaki
sem in AppleGFXReadMemoryJob is an one-shot event so it can be converted
into QemuEvent, which is more specialized for such a use case.
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
Link: https://lore.kernel.org/r/20250529-event-v5-10-53b285203...@daynix.
On Thu, 1 May 2025 23:04:52 +0200
Philippe Mathieu-Daudé wrote:
> The pc_compat_2_9[] array was only used by the pc-q35-2.9
> and pc-i440fx-2.9 machines, which got removed. Remove it.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Igor Mammedov
> ---
> include/hw/i386/pc.h | 3 ---
On Thu, 1 May 2025 23:04:53 +0200
Philippe Mathieu-Daudé wrote:
> The hw_compat_2_9[] array was only used by the pc-q35-2.9 and
> pc-i440fx-2.9 machines, which got removed. Remove it.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Igor Mammedov
> ---
> include/hw/boards.h | 3 ---
>
On Thu, 1 May 2025 23:04:55 +0200
Philippe Mathieu-Daudé wrote:
> The GenPCIERootPort::migrate_msix boolean was only set in
> the hw_compat_2_9[] array, via the 'x-migrate-msix=false'
> property. We removed all machines using that array, lets
> remove that property and all the code around it.
>
On Thu, 1 May 2025 23:04:48 +0200
Philippe Mathieu-Daudé wrote:
> VIRTIO_PCI_FLAG_INIT_PM was only used by the hw_compat_2_8[]
> array, via the 'x-pcie-pm-init=off' property. We removed all
> machines using that array, lets remove all the code around
> VIRTIO_PCI_FLAG_INIT_PM (see commit 9a4c0e2
From: Peter Maydell
Add some fma test cases that check for correct handling of FTZ and
for the flag that indicates that the input denormal was consumed.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Reviewed-by: Zhao Liu
Link:
https://lore.kernel.org/r/20250519145114.2786534-5-
Hi, thanks for responding!
Usual flow was
source build/pyvenv/bin/activate
export PYTHONBREAKPOINT="ipdb.set_trace"
export
QEMU_TEST_QEMU_BINARY=/home/lukvladimir/dev/qemu/build/qemu-system-aarch64
If missing python packages / avocado
pip install -e python/
pip install avocado
Daniel P. Berrangé writes:
> On Mon, Jun 02, 2025 at 10:38:05PM -0300, Fabiano Rosas wrote:
>> Add a QAPI command feature "capabilities" that can be queried by the
>> client to check that the parameters commands now also support
>> capabilities.
>>
>> Signed-off-by: Fabiano Rosas
>> ---
>> qap
On Thu, Jun 05, 2025 at 06:08:08PM -0500, Jaehoon Kim wrote:
> When the source VM attempts to connect to the destination VM's Unix
> domain socket(cpr.sock) during CPR transfer, the socket file might not
> yet be exist if the destination side hasn't completed the bind
> operation. This can lead to
On 6/6/2025 9:53 AM, Daniel P. Berrangé wrote:
On Thu, Jun 05, 2025 at 06:08:08PM -0500, Jaehoon Kim wrote:
When the source VM attempts to connect to the destination VM's Unix
domain socket(cpr.sock) during CPR transfer, the socket file might not
yet be exist if the destination side hasn't compl
On 6/6/2025 8:40 AM, Fabiano Rosas wrote:
Jaehoon Kim writes:
When the source VM attempts to connect to the destination VM's Unix
domain socket(cpr.sock) during CPR transfer, the socket file might not
yet be exist if the destination side hasn't completed the bind
operation. This can lead to co
On 6/6/25 10:37, Peter Maydell wrote:
On Thu, 5 Jun 2025 at 20:35, Philippe Mathieu-Daudé wrote:
Eradicate alloca() uses on system code, then enable
-Walloca to prevent new ones to creep back in.
Philippe Mathieu-Daudé (4):
hw/gpio/pca9552: Avoid using g_newa()
backends/tpmL Avoid using
On Fri, Jun 06, 2025 at 03:02:34AM -0400, Shaoqin Huang wrote:
> Now the ramfb will load the vgabios-ramfb.bin unconditionally, but only
> the x86 need the vgabios-ramfb.bin, this can cause that when use the
> release package on arm64 it can't find the vgabios-ramfb.bin.
>
> Because only seabios w
On Thu, 5 Jun 2025 at 20:35, Philippe Mathieu-Daudé wrote:
>
> Eradicate alloca() uses on system code, then enable
> -Walloca to prevent new ones to creep back in.
>
> Philippe Mathieu-Daudé (4):
> hw/gpio/pca9552: Avoid using g_newa()
> backends/tpmL Avoid using g_alloca()
> tests/unit/test
Philippe Mathieu-Daudé writes:
> Eradicate alloca() uses on system code, then enable
> -Walloca to prevent new ones to creep back in.
Should we also mention it in style.rst:
Use of the ``malloc/free/realloc/calloc/valloc/memalign/posix_memalign``
APIs is not allowed in the QEMU codebase. In
On 6/6/25 11:28, Xiaoyao Li wrote:
On 6/6/2025 5:19 PM, Philippe Mathieu-Daudé wrote:
On 6/6/25 10:49, Xiaoyao Li wrote:
On 6/3/2025 10:53 PM, Paolo Bonzini wrote:
On 6/3/25 13:26, Philippe Mathieu-Daudé wrote:
On 3/6/25 05:04, Xiaoyao Li wrote:
On 6/3/2025 1:31 AM, Cédric Le Goater wrote:
On 2025/06/05 20:57, Alex Bennée wrote:
Akihiko Odaki writes:
On 2025/06/03 20:01, Alex Bennée wrote:
QOM objects can be embedded in other QOM objects and managed as part
of their lifetime but this isn't the case for
virtio_gpu_virgl_hostmem_region. However before we can split it out we
need
Jaehoon Kim writes:
> When the source VM attempts to connect to the destination VM's Unix
> domain socket(cpr.sock) during CPR transfer, the socket file might not
> yet be exist if the destination side hasn't completed the bind
> operation. This can lead to connection failures when running tests
On Thu, 1 May 2025 23:04:54 +0200
Philippe Mathieu-Daudé wrote:
> The VirtIONet::mtu_bypass_backend boolean was only set in
> the hw_compat_2_9[] array, via the 'x-mtu-bypass-backend=off'
> property. We removed all machines using that array, lets remove
> that property and all the code around it
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