* Babu Moger (babu.mo...@amd.com) wrote:
> Add CPUID bit indicates that a WRMSR to MSR_FS_BASE, MSR_GS_BASE, or
> MSR_KERNEL_GS_BASE is non-serializing amd PREFETCHI that the indicates
> support for IC prefetch.
>
> CPUID_Fn80000021_EAX
> Bit Feature description
> 20 Indicates support for IC prefetch.
> 1 FsGsKernelGsBaseNonSerializing.
I'm curious about this:
a) Is this new CPUs are non-serialising on that write?
b) If so, what happens if you run existing kernels/firmware on them?
c) Bonus migration question; what happens if you live migrate from a host
that claims to be serialising to one that has the extra non-serialising
flag but is disabled in the emulated CPU model.
Dave
> WRMSR to FS_BASE, GS_BASE and KernelGSbase are non-serializing.
>
> Link:
> https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/programmer-references/57238.zip
> Signed-off-by: Babu Moger <babu.mo...@amd.com>
> Reviewed-by: Maksim Davydov <davydov-...@yandex-team.ru>
> Reviewed-by: Zhao Liu <zhao1....@intel.com>
> ---
> target/i386/cpu.c | 4 ++--
> target/i386/cpu.h | 4 ++++
> 2 files changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 98fad3a2f9..741be0eaa8 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -1239,12 +1239,12 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
> [FEAT_8000_0021_EAX] = {
> .type = CPUID_FEATURE_WORD,
> .feat_names = {
> - "no-nested-data-bp", NULL, "lfence-always-serializing", NULL,
> + "no-nested-data-bp", "fs-gs-base-ns",
> "lfence-always-serializing", NULL,
> NULL, NULL, "null-sel-clr-base", NULL,
> "auto-ibrs", NULL, NULL, NULL,
> NULL, NULL, NULL, NULL,
> NULL, NULL, NULL, NULL,
> - NULL, NULL, NULL, NULL,
> + "prefetchi", NULL, NULL, NULL,
> "eraps", NULL, NULL, "sbpb",
> "ibpb-brtype", "srso-no", "srso-user-kernel-no", NULL,
> },
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index 4f8ed8868e..d251e32ae9 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -1070,12 +1070,16 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU
> *cpu, FeatureWord w);
>
> /* Processor ignores nested data breakpoints */
> #define CPUID_8000_0021_EAX_NO_NESTED_DATA_BP (1U << 0)
> +/* WRMSR to FS_BASE, GS_BASE, or KERNEL_GS_BASE is non-serializing */
> +#define CPUID_8000_0021_EAX_FS_GS_BASE_NS (1U << 1)
> /* LFENCE is always serializing */
> #define CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING (1U << 2)
> /* Null Selector Clears Base */
> #define CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE (1U << 6)
> /* Automatic IBRS */
> #define CPUID_8000_0021_EAX_AUTO_IBRS (1U << 8)
> +/* Indicates support for IC prefetch */
> +#define CPUID_8000_0021_EAX_PREFETCHI (1U << 20)
> /* Enhanced Return Address Predictor Scurity */
> #define CPUID_8000_0021_EAX_ERAPS (1U << 24)
> /* Selective Branch Predictor Barrier */
> --
> 2.34.1
>
>
--
-----Open up your eyes, open up your mind, open up your code -------
/ Dr. David Alan Gilbert | Running GNU/Linux | Happy \
\ dave @ treblig.org | | In Hex /
\ _________________________|_____ http://www.treblig.org |_______/
