[PATCH v3 39/69] target/arm: Introduce gen_gvec_cnt, gen_gvec_rbit

Add gvec interfaces for CNT and RBIT operations. Use ctpop8 for CNT and revbit+bswap for RBIT. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.h | 4 ++-- target/arm/tcg/translate.h | 4 target/arm/tcg/gengvec.c| 16 +

[PATCH v3 30/69] target/arm: Convert FRINT{32, 64}[ZX] (scalar) to decodetree

Remove handle_fp_1src_single and handle_fp_1src_double as these were the last insns decoded by those functions. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 146 - target/arm/tcg/a64.decode | 5 ++ 2 file

[PATCH v3 62/69] target/arm: Convert [US]CVTF (vector) to decodetree

Remove handle_simd_intfp_conv and handle_simd_shift_intfp_conv as these were the last insns decoded by those functions. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.h| 3 + target/arm/tcg/translate-a64.c | 201 ++---

Re: [RFC PATCH 5/5] hw/arm/virt-acpi-build: Add IORT RMR regions to handle MSI nested binding

On Wed, Dec 11, 2024 at 09:20:20AM -0800, Nicolin Chen wrote: > On Wed, Dec 11, 2024 at 09:11:12AM -0400, Jason Gunthorpe wrote: > > On Tue, Dec 10, 2024 at 05:28:17PM -0800, Nicolin Chen wrote: > > > > I would ideally turn it around and provide that range information to > > > > the kernel and tota

Re: [PATCH 1/2] s390x/pci: add support for guests that request direct mapping

On 09/12/2024 20.29, Matthew Rosato wrote: When receiving a guest mpcifc(4) or mpcifc(6) instruction without the T bit set, treat this as a request to perform direct mapping instead of address translation. In order to facilitiate this, pin the entirety of s/facilitiate/facilitate/ guest memo

Re: [PATCH 14/26] rust: qom: move bridge for TypeInfo functions out of pl011

> Generally: > > - embedded objects will have to be initialized in instance_init unless they > are Options I see, at least for HPETTimer array, I need to prepare all of them in instance_init()... > - if you don't need properties you can choose between post_init and > realize, if you need propert

Re: [PATCH v3 42/69] target/arm: Introduce gen_gvec_rev{16,32,64}

On 11/12/24 17:30, Richard Henderson wrote: Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 6 +++ target/arm/tcg/gengvec.c| 58 ++ target/arm/tcg/translate-neon.c | 88 +++-- 3 files

[PULL 45/49] rust: qdev: move device_class_init! body to generic function, ClassInitImpl implementation to macro

Use a trait to access the former parameters to device_class_init!. This allows hiding the details of the class_init implementation behind a generic function and makes higher-level functionality available from qemu_api. The implementation of ClassInitImpl is then the same for all devices and is eas

[PATCH v3 44/69] target/arm: Move helper_neon_addlp_{s8, s16} to neon_helper.c

Move from helper-a64.c to neon_helper.c so that these functions are available for arm32 code as well. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.h | 2 ++ target/arm/tcg/helper-a64.h | 2 -- target/arm/tcg/helper-a64.c | 43 ---

[PATCH v3 64/69] target/arm: Convert FCVT* (vector, integer) to decodetree

Remove handle_2misc_64 as these were the last insns decoded by that function. Remove helper_advsimd_f16to[su]inth as unused; we now always go through helper_vfp_to[su]hh or a specialized vector function instead. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.

[PATCH v3 10/69] target/arm: Convert XPAC[ID] to decodetree

Remove disas_data_proc_1src, as these were the last insns decoded by that function. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 99 +- target/arm/tcg/a64.decode | 3 ++ 2 files changed, 16 insert

[PULL 37/49] rust: cell: add BQL-enforcing RefCell variant

Similar to the existing BqlCell, introduce a custom interior mutability primitive that resembles RefCell but accounts for QEMU's threading model. Borrowing the RefCell requires proving that the BQL is held, and attempting to access without the BQL is a runtime panic. Almost all of the code was tak

[PATCH v3 02/69] target/arm: Convert UDIV, SDIV to decodetree

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 64 +- target/arm/tcg/a64.decode | 7 2 files changed, 39 insertions(+), 32 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/

[PATCH v3 09/69] target/arm: Convert PAC[ID]*, AUT[ID]* to decodetree

This includes PACIA, PACIZA, PACIB, PACIZB, PACDA, PACDZA, PACDB, PACDZB, AUTIA, AUTIZA, AUTIB, AUTIZB, AUTDA, AUTDZA, AUTDB, AUTDZB. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 173 + target/arm/tcg/a64.decode

[PATCH v3 42/69] target/arm: Introduce gen_gvec_rev{16,32,64}

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 6 +++ target/arm/tcg/gengvec.c| 58 ++ target/arm/tcg/translate-neon.c | 88 +++-- 3 files changed, 81 insertions(+), 71 deletions(-) diff

[PATCH v3 28/69] target/arm: Convert FRINT[NPMSAXI] (scalar) to decodetree

Remove handle_fp_1src_half as these were the last insns decoded by that function. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 117 +++-- target/arm/tcg/a64.decode | 8 +++ 2 files changed, 46 insertions(+),

[PULL 03/49] rust: allow using build-root bindings.rs from cargo

Right now, using cargo with QEMU requires copying by hand the bindings.rs to the source tree. Instead, we can use an include file to escape the cage of cargo's mandated source directory structure. By running cargo within meson's "devenv" and adding a MESON_BUILD_ROOT environment variable, it is e

[PATCH v3 04/69] target/arm: Convert CRC32, CRC32C to decodetree

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 101 + target/arm/tcg/a64.decode | 12 2 files changed, 53 insertions(+), 60 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm

[PATCH v3 63/69] target/arm: Convert FCVTZ[SU] (vector, fixed-point) to decodetree

Remove handle_simd_shift_fpint_conv and disas_simd_shift_imm as these were the last insns decoded by those functions. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.h| 4 + target/arm/tcg/translate-a64.c | 160 +++-- t

[PATCH v3 34/69] target/arm: Convert handle_fmov to decodetree

Remove disas_fp_int_conv and disas_data_proc_fp as these were the last insns decoded by those functions. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 232 ++--- target/arm/tcg/a64.decode | 14 ++ 2 files chang

[PATCH v3 05/69] target/arm: Convert SUBP, IRG, GMI to decodetree

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 94 +++--- target/arm/tcg/a64.decode | 7 +++ 2 files changed, 59 insertions(+), 42 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/t

Re: [PULL 00/24] aspeed queue

legoater/qemu/ tags/pull-aspeed-20241211 > > for you to fetch changes up to 124f4dc0d832c1bf3a4513c05a2b93bac0a5fac0: > > test/qtest/ast2700-smc-test: Support to test AST2700 (2024-12-11 07:25:53 > +0100) > > >

Re: [PULL for-9.2 0/1] 9p queue 2024-12-10

On Tue, 10 Dec 2024 at 10:11, Christian Schoenebeck wrote: > > The following changes since commit 1cf9bc6eba7506ab6d9de635f224259225f63466: > > Update version for v9.2.0-rc3 release (2024-12-03 17:56:12 +) > > are available in the Git repository at: > > https://github.com/cschoenebeck/qemu

Re: [PATCH V4 09/19] migration: incoming channel

On 12/9/2024 7:12 AM, Markus Armbruster wrote: Steven Sistare writes: On 12/5/2024 10:23 AM, Markus Armbruster wrote: Steve Sistare writes: Extend the -incoming option to allow an @MigrationChannel to be specified. This allows channels other than 'main' to be described on the command line,

[PATCH v2] hw/virtio: Fix check available index on virtio loading

From: Wafer Xie The virtio-1.2 specification writes: 2.7.6 The Virtqueue Available Ring: "idx field indicates where the driver would put the next descriptor entry in the ring (modulo the queue size). This starts at 0, and increases" The idx will increase from 0 to 0x and repeat, So idx may

Re: [PATCH 13/26] rust: qom: automatically use Drop trait to implement instance_finalize

On Tue, Dec 10, 2024 at 4:58 PM Zhao Liu wrote: > Great idea. It nicely balances the differences between Rust and C QOM > conventions. Except it does not work. :( Suppose you have pub struct MySuperclass { parent: DeviceState, field: Box, ... }

Re: [PATCH v2] hw/virtio: Fix check available index on virtio loading

On Wed, Dec 11, 2024 at 1:34 PM Wafer wrote: > > From: Wafer Xie > > The virtio-1.2 specification writes: > > 2.7.6 The Virtqueue Available Ring: > "idx field indicates where the driver would put the next descriptor entry > in the ring (modulo the queue size). This starts at 0, and increases" > >

[PATCH v7 0/2] target/riscv: rvv: reduce the overhead for simple RISC-V vector unit-stride loads and stores

Changes since v6: - Limit access size to element size to address Max Chou's review. - Fix a typo in the name of a function that this patch now calls. With access size limited to element size this patch still provides a significant speedup. The `memcpy` benchmark from: https://github.com/e

[PATCH v7 1/2] target/riscv: rvv: fix typo in vext continuous ldst function names

Replace `continus` with `continuous`. Signed-off-by: Craig Blackmore --- target/riscv/vector_helper.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index a85dd1d200..0f57e48cc5 100644 --- a/target/riscv/

[PATCH v7 2/2] target/riscv: rvv: speed up small unit-stride loads and stores

Calling `vext_continuous_ldst_tlb` for load/stores smaller than 12 bytes significantly improves performance. Co-authored-by: Helene CHELIN Co-authored-by: Paolo Savini Co-authored-by: Craig Blackmore Signed-off-by: Helene CHELIN Signed-off-by: Paolo Savini Signed-off-by: Craig Blackmore ---

Re: [RFC PATCH 5/5] hw/arm/virt-acpi-build: Add IORT RMR regions to handle MSI nested binding

On Tue, Dec 10, 2024 at 05:28:17PM -0800, Nicolin Chen wrote: > > I would ideally turn it around and provide that range information to > > the kernel and totally ignore the SW_MSI reserved region once > > userspace provides it. > > Hmm.. that sounds like a uAPI for vITS range..but yes.. It contro

Re: [PATCH v3 16/24] migration/multifd: Send final SYNC only after device state is complete

On Wed, Dec 11, 2024 at 12:05:40AM +0100, Maciej S. Szmigiero wrote: > > I sent two small patches here: > > > > https://lore.kernel.org/r/20241205185303.897010-1-pet...@redhat.com > > > > The 1st patch should fix the SYNC message hang for 637280aeb2 that I did. > > The 2nd patch introduced the fl

[PATCH] tcg/riscv: Fix StoreStore barrier generation

On RISC-V to StoreStore barrier corresponds `fence w, w` not `fence r, r` Signed-off-by: Denis Tomashev Signed-off-by: Roman Artemev --- tcg/riscv/tcg-target.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index f

[PATCH v1 0/1] Add vtype.vill FIELD macro definition

Hi, all: According to the "The RISC-V Instruction Set Manual Volume I: Unprivileged Architecture" Version 20240411, Section 31.3.4 "Vector type register, vtype", and Table 40 "vtype register layout", this patch adds the definition for the vill field of the vtype register. The bit position for vill

[RFC PATCH v5 0/1] target/riscv: rvv: Use wider accesses for unit stride load/store

Changes since v4: - Split into a seperate submission to simplify review - Use load/store atomic functions as suggested by Richard Henderson - Do 8, 4, 2 byte atomic ldst for sizes smaller than 16 bytes This patch now uses the atomic ldst functions from accel/tcg/ldst_atomicity.c.inc to ensure elem

[RFC PATCH v5 1/1] target/riscv: rvv: Use wider accesses for unit stride load/store

Use atomic load/store functions to access multiple elements from host. Co-authored-by: Paolo Savini Signed-off-by: Paolo Savini Signed-off-by: Craig Blackmore --- target/riscv/trace-events| 12 + target/riscv/vector_helper.c | 95 +--- 2 files changed,

Re: [PATCH v1 1/1] target/riscv: add VILL field for vtype register macro definition

On 12/11/24 07:47, Chao Liu wrote: Signed-off-by: Chao Liu --- target/riscv/cpu.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 284b112821..fc286484b8 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -170,7 +170,

[PATCH v1 1/1] target/riscv: add VILL field for vtype register macro definition

Signed-off-by: Chao Liu --- target/riscv/cpu.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 284b112821..fc286484b8 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -170,7 +170,8 @@ FIELD(VTYPE, VSEW, 3, 3) FIELD(VT

Re: [PATCH v7 2/2] target/riscv: rvv: speed up small unit-stride loads and stores

On 2024/12/11 8:51 PM, Craig Blackmore wrote: Calling `vext_continuous_ldst_tlb` for load/stores smaller than 12 bytes significantly improves performance. Co-authored-by: Helene CHELIN Co-authored-by: Paolo Savini Co-authored-by: Craig Blackmore Signed-off-by: Helene CHELIN Signed-off-by: P

Re: [PATCH 1/2] s390x/pci: add support for guests that request direct mapping

On 12/9/24 20:29, Matthew Rosato wrote: When receiving a guest mpcifc(4) or mpcifc(6) instruction without the T bit set, treat this as a request to perform direct mapping instead of address translation. In order to facilitiate this, pin the entirety of guest memory into the host iommu. Subseque

[PATCH v2 0/6] target/arm: Implement FEAT_XS

Based-on: 20241210160452.2427965-1-peter.mayd...@linaro.org ("target/arm: Pull TLBI insns out to their own source file") The FEAT_XS feature was introduced in ARMv8.7: it adds a new memory attribute XS which indicates that a memory access could take longer than usual to complete, and also adds ins

[PATCH v2 5/6] target/arm: Enable FEAT_XS for the max cpu

From: Manos Pitsidianakis Add FEAT_XS feature report value in max cpu's ID_AA64ISAR1 sys register. Signed-off-by: Manos Pitsidianakis Signed-off-by: Peter Maydell [PMM: Add entry for FEAT_XS to documentation] Reviewed-by: Richard Henderson --- docs/system/arm/emulation.rst | 1 + target/arm/

[PATCH v2 1/6] target/arm: Implement fine-grained-trap handling for FEAT_XS

FEAT_XS introduces a set of new TLBI maintenance instructions with an "nXS" qualifier. These behave like the stardard ones except that they do not wait for memory accesses with the XS attribute to complete. They have an interaction with the fine-grained-trap handling: the FGT bits that a hypervis

[PATCH v2 3/6] target/arm: Add ARM_CP_ADD_TLBI_NXS type flag to TLBI insns

Add the ARM_CP_ADD_TLBI_NXS to the TLBI insns with an NXS variant. This is every AArch64 TLBI encoding except for the four FEAT_RME TLBI insns. Signed-off-by: Peter Maydell --- target/arm/tcg/tlb-insns.c | 202 +++-- 1 file changed, 124 insertions(+), 78 deletions

[PATCH v2 4/6] target/arm: Add decodetree entry for DSB nXS variant

From: Manos Pitsidianakis The DSB nXS variant is always both a reads and writes request type. Ignore the domain field like we do in plain DSB and perform a full system barrier operation. The DSB nXS variant is part of FEAT_XS made mandatory from Armv8.7. Signed-off-by: Manos Pitsidianakis [PMM

[PATCH v2 6/6] tests/tcg/aarch64: add system test for FEAT_XS

From: Manos Pitsidianakis Add system test to make sure FEAT_XS is enabled for max cpu emulation and that QEMU doesn't crash when encountering an NXS instruction variant. Signed-off-by: Manos Pitsidianakis [PMM: In ISAR field test, mask with 0xf, not 0xff; use < rather than an equality test to

[PATCH v2 2/6] target/arm: Add ARM_CP_ADD_TLBI_NXS type flag for NXS insns

All of the TLBI insns with an NXS variant put that variant at the same encoding but with a CRn field that is one greater than for the original TLBI insn. To avoid having to define every TLBI insn effectively twice, once in the normal way and once in a set of cpreg arrays that are only registered w

Re: [PATCH 0/2] Misc Hexagon QOL

On 12/6/2024 10:01 AM, Anton Johansson via wrote: Separate submission of patches 35 and 37 from the helper-to-tcg patchset: https://lore.kernel.org/qemu-devel/20241121014947.18666-1-a...@rev.ng/ Anton Johansson (2): target/hexagon: Use argparse in all python scripts target/hexagon: M

Re: [PATCH v2] Hexagon (target/hexagon) Remove HEX_DEBUG/HEX_DEBUG_LOG

On 12/4/2024 1:59 PM, Brian Cain wrote: On 11/5/2024 10:27 AM, Taylor Simpson wrote: All Hexagon debugging is now done with QEMU mechanisms (e.g., -d in_asm) or with a connected debugger (lldb). Signed-off-by: Taylor Simpson Reviewed-by: Matheus Tavares Bernardino --- I was wondering why

Re: [PATCH v3 1/4] Add support for emulation of CRC32 instructions

Hi, A kind remind/ping on the patch. Before we send v3, do you have any comments on this patch? Kind regards, Aleksandar Rakic

Re: [PATCH v3 2/4] Skip NaN mode check for soft-float

Hi, A kind remind/ping on the patch. Before we send v3, do you have any comments on this patch? Kind regards, Aleksandar Rakic

Re: [PATCH v9 0/6] Add Smrnmi support

Hi, A gentle ping on this. Regards, Frank Chang 於 2024年11月22日 週五 上午11:23寫道： > > From: Frank Chang > > This patchset added support for Smrnmi Extension in RISC-V. > > There are four new CSRs and one new instruction added to allow NMI to be > resumable in RISC-V, which are: > >

Re: [PATCH v3 3/4] target/mips: Enable MSA ASE using a CLI flag

Hi, A kind remind/ping on the patch. Before we send v3, do you have any comments on this patch? Kind regards, Aleksandar Rakic

RE: [RFC PATCH 4/5] hw/arm/virt-acpi-build: Build IORT with multiple SMMU nodes

Hi Nicolin, > -Original Message- > From: Nicolin Chen > Sent: Tuesday, December 10, 2024 8:48 PM > To: Shameerali Kolothum Thodi > Cc: eric.au...@redhat.com; qemu-...@nongnu.org; qemu- > de...@nongnu.org; peter.mayd...@linaro.org; j...@nvidia.com; > ddut...@redhat.com; Linuxarm ; Wangzho

No display in Xen PV guests: "This VM has no graphic display device."

Hello everyone, We've found an issue that manifests in Xen PV guests. We have encountered it when testing our (SUSE and openSUSE) packaged version of 9.1.x, but I've been able to reproduce it even using the upstream master branch. QEMU 8.2.8 works fine, so something happened during 9.0 or 9.1 dev

Re: [PATCH 1/2] s390x/pci: add support for guests that request direct mapping

On 12/11/24 9:40 AM, Cédric Le Goater wrote: > On 12/9/24 20:29, Matthew Rosato wrote: >>   static int reg_ioat(CPUS390XState *env, S390PCIBusDevice *pbdev, ZpciFib >> fib, >>   uintptr_t ra) >>   { >> @@ -1008,7 +1036,7 @@ static int reg_ioat(CPUS390XState *env, >> S390PCIBu

Re: [PATCH v2 1/6] target/arm: Implement fine-grained-trap handling for FEAT_XS

On 12/11/24 08:44, Peter Maydell wrote: FEAT_XS introduces a set of new TLBI maintenance instructions with an "nXS" qualifier. These behave like the stardard ones except that they do not wait for memory accesses with the XS attribute to complete. They have an interaction with the fine-grained-t

Re: [PATCH v2 23/69] target/arm: Fix decode of fp16 vector fabs, fneg

On Tue, 10 Dec 2024 at 16:19, Richard Henderson wrote: > > These opcodes are only supported as vector operations, > not as advsimd scalar. Set only_in_vector, and remove > the unreachable implementation of scalar fneg. > > Reported-by: Peter Maydell > Signed-off-by: Richard Henderson > --- > t

Re: [PATCH v2 2/6] target/arm: Add ARM_CP_ADD_TLBI_NXS type flag for NXS insns

On 12/11/24 08:44, Peter Maydell wrote: All of the TLBI insns with an NXS variant put that variant at the same encoding but with a CRn field that is one greater than for the original TLBI insn. To avoid having to define every TLBI insn effectively twice, once in the normal way and once in a set

[PATCH v2 0/1] Add vtype.vill FIELD macro definition

Hi, all: I improve compatibility with RV32 and RV64 by adjusting the FIELD definition of vtype.vill. PATCH v1: https://lore.kernel.org/qemu-devel/cover.1733922709.git.lc00...@tecorigin.com/T Chao Liu (1): target/riscv: add VILL field for vtype register macro definition target/riscv/cpu.h | 3

Re: [PATCH v2 3/6] target/arm: Add ARM_CP_ADD_TLBI_NXS type flag to TLBI insns

On 12/11/24 08:44, Peter Maydell wrote: Add the ARM_CP_ADD_TLBI_NXS to the TLBI insns with an NXS variant. This is every AArch64 TLBI encoding except for the four FEAT_RME TLBI insns. Signed-off-by: Peter Maydell --- target/arm/tcg/tlb-insns.c | 202 +++-- 1 fi

[PATCH v2 1/1] target/riscv: add VILL field for vtype register macro definition

Signed-off-by: Chao Liu --- target/riscv/cpu.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 284b112821..0d74ee4581 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -170,7 +170,8 @@ FIELD(VTYPE, VSEW, 3, 3) FIELD(VT

Re: [PATCH v2 4/6] target/arm: Add decodetree entry for DSB nXS variant

On 12/11/24 08:44, Peter Maydell wrote: From: Manos Pitsidianakis The DSB nXS variant is always both a reads and writes request type. Ignore the domain field like we do in plain DSB and perform a full system barrier operation. The DSB nXS variant is part of FEAT_XS made mandatory from Armv8.7.

Re: [PATCH v2 24/69] target/arm: Convert FMOV, FABS, FNEG (scalar) to decodetree

On Tue, 10 Dec 2024 at 16:23, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/tcg/translate-a64.c | 105 +++-- > target/arm/tcg/a64.decode | 7 +++ > 2 files changed, 81 insertions(+), 31 deletions(-) Reviewed-by: Peter Maydell

Re: [PATCH v2 29/69] target/arm: Convert BFCVT to decodetree

On Tue, 10 Dec 2024 at 16:21, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/tcg/translate-a64.c | 26 +++--- > target/arm/tcg/a64.decode | 3 +++ > 2 files changed, 10 insertions(+), 19 deletions(-) > Reviewed-by: Peter Maydell than

Re: [PATCH v2 43/69] target/arm: Convert handle_rev to decodetree

On Tue, 10 Dec 2024 at 16:26, Richard Henderson wrote: > > This includes REV16, REV32, REV64. > > Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell thanks -- PMM

Re: [PATCH v2 1/1] target/riscv: add VILL field for vtype register macro definition

On 12/11/24 09:48, Chao Liu wrote: Signed-off-by: Chao Liu --- target/riscv/cpu.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 284b112821..0d74ee4581 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -170,7 +170,

Re: [RFC v4 0/5] Add packed virtqueue to shadow virtqueue

Hi, Thank you for your reply. On 12/10/24 2:57 PM, Eugenio Perez Martin wrote: On Thu, Dec 5, 2024 at 9:34 PM Sahil Siddiq wrote: Hi, There are two issues that I found while trying to test my changes. I thought I would send the patch series as well in case that helps in troubleshooting. I h

Re: [RFC v4 2/5] vhost: Write descriptors to packed svq

Hi, On 12/10/24 2:24 PM, Eugenio Perez Martin wrote: On Thu, Dec 5, 2024 at 9:35 PM Sahil Siddiq wrote: This commit is the first in a series to add support for packed virtqueues in vhost_shadow_virtqueue. This patch implements the insertion of available buffers in the descriptor area. It tak

Re: [RFC v4 3/5] vhost: Data structure changes to support packed vqs

Hi, On 12/10/24 2:25 PM, Eugenio Perez Martin wrote: On Thu, Dec 5, 2024 at 9:35 PM Sahil Siddiq wrote: Introduce "struct vring_packed". Modify VhostShadowVirtqueue so it can support split and packed virtqueue formats. This patch should be before the previous one or it does not compile, i

Re: [PATCH v2 53/69] target/arm: Implement gen_gvec_fabs, gen_gvec_fneg

On Tue, 10 Dec 2024 at 16:26, Richard Henderson wrote: > > Move the current implementation out of translate-neon.c, > and extend to handle all element sizes. > > Signed-off-by: Richard Henderson > --- > target/arm/tcg/translate.h | 6 ++ > target/arm/tcg/gengvec.c| 14 +

Re: [PATCH v2 57/69] target/arm: Convert FCVT* (vector, integer) scalar to decodetree

On Tue, 10 Dec 2024 at 16:27, Richard Henderson wrote: > > Arm silliness with naming, the scalar insns described > as part of the vector instructions, as separate from > the "regular" scalar insns which output to general registers. > > Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell

Re: [PATCH v2 58/69] target/arm: Convert FCVT* (vector, fixed-point) scalar to decodetree

On Tue, 10 Dec 2024 at 16:27, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/tcg/translate-a64.c | 4 +--- > target/arm/tcg/a64.decode | 19 +++ > 2 files changed, 20 insertions(+), 3 deletions(-) Reviewed-by: Peter Maydell thanks -- PMM

Re: [PATCH v2 60/69] target/arm: Convert [US]CVTF (vector, fixed-point) scalar to decodetree

On Tue, 10 Dec 2024 at 16:26, Richard Henderson wrote: > > Remove disas_simd_scalar_shift_imm as these were the > last insns decoded by that function. > > Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell thanks -- PMM

Re: [PATCH v2 62/69] target/arm: Convert [US]CVTF (vector) to decodetree

On Tue, 10 Dec 2024 at 16:28, Richard Henderson wrote: > > Remove handle_simd_intfp_conv and handle_simd_shift_intfp_conv > as these were the last insns decoded by those functions. > > Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell thanks -- PMM

Re: [PATCH 13/26] rust: qom: automatically use Drop trait to implement instance_finalize

On Wed, Dec 11, 2024 at 01:42:32PM +0100, Paolo Bonzini wrote: > Date: Wed, 11 Dec 2024 13:42:32 +0100 > From: Paolo Bonzini > Subject: Re: [PATCH 13/26] rust: qom: automatically use Drop trait to > implement instance_finalize > > On Tue, Dec 10, 2024 at 4:58 PM Zhao Liu wrote: > > Great idea.

Re: [PATCH v2 63/69] target/arm: Convert FCVTZ[SU] (vector, fixed-point) to decodetree

On Tue, 10 Dec 2024 at 16:29, Richard Henderson wrote: > > Remove handle_simd_shift_fpint_conv and disas_simd_shift_imm > as these were the last insns decoded by those functions. > > Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell thanks -- PMM

Re: [PATCH v2 23/69] target/arm: Fix decode of fp16 vector fabs, fneg

On 12/11/24 09:44, Peter Maydell wrote: On Tue, 10 Dec 2024 at 16:19, Richard Henderson wrote: These opcodes are only supported as vector operations, not as advsimd scalar. Set only_in_vector, and remove the unreachable implementation of scalar fneg. Reported-by: Peter Maydell Signed-off-by

Re: [PATCH v2 64/69] target/arm: Convert FCVT* (vector, integer) to decodetree

On Tue, 10 Dec 2024 at 16:28, Richard Henderson wrote: > > Remove handle_2misc_64 as these were the last insns decoded > by that function. Remove helper_advsimd_f16to[su]inth as unused; > we now always go through helper_vfp_to[su]hh or a specialized > vector function instead. > > Signed-off-by: R

Re: [PATCH v2 67/69] target/arm: Introduce gen_gvec_urecpe, gen_gvec_ursqrte

On Tue, 10 Dec 2024 at 16:26, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/helper.h | 3 +++ > target/arm/tcg/translate.h | 5 + > target/arm/tcg/gengvec.c| 16 > target/arm/tcg/translate-neon.c | 4 ++-- > targ

Re: [PATCH v2 68/69] target/arm: Convert URECPE and URSQRTE to decodetree

On Tue, 10 Dec 2024 at 16:25, Richard Henderson wrote: > > Remove handle_2misc_reciprocal as these were the last > insns decoded by that function. > > Signed-off-by: Richard Henderson > --- Reviewed-by: Peter Maydell thanks -- PMM

[PULL 35/72] target/m68k: In frem helper, initialize local float_status from env->fp_status

In the frem helper, we have a local float_status because we want to execute the floatx80_div() with a custom rounding mode. Instead of zero-initializing the local float_status and then having to set it up with the m68k standard behaviour (including the NaN propagation rule and copying the rounding

[PULL 00/72] target-arm queue

Open 10.0 development tree (2024-12-10 17:41:17 +) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20241211 for you to fetch changes up to 1abe28d519239eea5cf9620bb13149423e5665f8: MAINTAINERS: Add correct email addres

[PULL 12/72] target/ppc: Set FloatInfZeroNaNRule explicitly

Set the FloatInfZeroNaNRule explicitly for the PPC target, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-8-peter.mayd...@linaro.org --- target/ppc/cpu_init.c | 7 +++ fpu/softfloat-spec

[PULL 10/72] target/arm: Set FloatInfZeroNaNRule explicitly

Set the FloatInfZeroNaNRule explicitly for the Arm target, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-6-peter.mayd...@linaro.org --- target/arm/cpu.c | 3 +++ fpu/softfloat-speciali

[PULL 31/72] fpu: Remove use_first_nan field from float_status

The use_first_nan field in float_status was an xtensa-specific way to select at runtime from two different NaN propagation rules. Now that xtensa is using the target-agnostic NaN propagation rule selection that we've just added, we can remove use_first_nan, because there is no longer any code that

[PULL 51/72] target/ppc: Set default NaN pattern explicitly

Set the default NaN pattern explicitly for ppc. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-46-peter.mayd...@linaro.org --- target/ppc/cpu_init.c | 4 1 file changed, 4 insertions(+) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init

[PULL 28/72] target/xtensa: Set Float3NaNPropRule explicitly

Set the Float3NaNPropRule explicitly for xtensa, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-24-peter.mayd...@linaro.org --- target/xtensa/fpu_helper.c | 2 ++ fpu/softfloat-specialize.c.inc | 8 ---

[PULL 30/72] target/hppa: Set Float3NaNPropRule explicitly

Set the Float3NaNPropRule explicitly for HPPA, and remove the ifdef from pickNaNMulAdd(). HPPA is the only target that was using the default branch of the ifdef ladder (other targets either do not use muladd or set default_nan_mode), so we can remove the ifdef fallback entirely now (allowing the "

[PULL 09/72] tests/fp: Explicitly set inf-zero-nan rule

Explicitly set a rule in the softfloat tests for the inf-zero-nan muladd special case. In meson.build we put -DTARGET_ARM in fpcflags, and so we should select here the Arm rule of float_infzeronan_dnan_if_qnan. Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell Message-id: 202412021313

[PULL 47/72] target/loongarch: Set default NaN pattern explicitly

Set the default NaN pattern explicitly for loongarch. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-42-peter.mayd...@linaro.org --- target/loongarch/tcg/fpu_helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/loongarch/tcg/fpu_he

[PULL 34/72] target/loongarch: Use normal float_status in fclass_s and fclass_d helpers

In target/loongarch's helper_fclass_s() and helper_fclass_d() we pass a zero-initialized float_status struct to float32_is_quiet_nan() and float64_is_quiet_nan(), with the cryptic comment "for snan_bit_is_one". This pattern appears to have been copied from target/riscv, where it is used because th

[PULL 38/72] target/ppc: Use env->fp_status in helper_compute_fprf functions

In the helper_compute_fprf functions, we pass a dummy float_status in to the is_signaling_nan() function. This is unnecessary, because we have convenient access to the CPU env pointer here and that is already set up with the correct values for the snan_bit_is_one and no_signaling_nans config settin

[PULL 02/72] hw/net/lan9118_phy: Reuse in imx_fec and consolidate implementations

From: Bernhard Beschow imx_fec models the same PHY as lan9118_phy. The code is almost the same with imx_fec having more logging and tracing. Merge these improvements into lan9118_phy and reuse in imx_fec to fix the code duplication. Some migration state how resides in the new device model which

[PULL 04/72] hw/net/lan9118_phy: Reuse MII constants

From: Bernhard Beschow Prefer named constants over magic values for better readability. Reviewed-by: Peter Maydell Signed-off-by: Bernhard Beschow Tested-by: Guenter Roeck Message-id: 20241102125724.532843-5-shen...@gmail.com Signed-off-by: Peter Maydell --- include/hw/net/mii.h | 6 +

[PULL 03/72] hw/net/lan9118_phy: Fix off-by-one error in MII_ANLPAR register

From: Bernhard Beschow Turns 0x70 into 0xe0 (== 0x70 << 1) which adds the missing MII_ANLPAR_TX and fixes the MSB of selector field to be zero, as specified in the datasheet. Fixes: 2a424990170b "LAN9118 emulation" Signed-off-by: Bernhard Beschow Tested-by: Guenter Roeck Reviewed-by: Peter May

[PULL 40/72] fpu: Allow runtime choice of default NaN value

Currently we hardcode the default NaN value in parts64_default_nan() using a compile-time ifdef ladder. This is awkward for two cases: * for single-QEMU-binary we can't hard-code target-specifics like this * for Arm FEAT_AFP the default NaN value depends on FPCR.AH (specifically the sign bit i

[PULL 08/72] softfloat: Allow runtime choice of inf * 0 + NaN result

IEEE 758 does not define a fixed rule for what NaN to return in the case of a fused multiply-add of inf * 0 + NaN. Different architectures thus do different things: * some return the default NaN * some return the input NaN * Arm returns the default NaN if the input NaN is quiet, and the input

[PULL 50/72] target/openrisc: Set default NaN pattern explicitly

Set the default NaN pattern explicitly for openrisc. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-45-peter.mayd...@linaro.org --- target/openrisc/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/openrisc/cpu.c b/target/openrisc/

[PULL 70/72] softfloat: Replace WHICH with RET in parts_pick_nan

From: Richard Henderson Replace the "index" selecting between A and B with a result variable of the proper type. This improves clarity within the function. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20241203203949.483774-12-richard.hender...@linaro.org Si

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