From: Manos Pitsidianakis <manos.pitsidiana...@linaro.org>
Add FEAT_XS feature report value in max cpu's ID_AA64ISAR1 sys register.
Signed-off-by: Manos Pitsidianakis <manos.pitsidiana...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
[PMM: Add entry for FEAT_XS to documentation]
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
---
docs/system/arm/emulation.rst | 1 +
target/arm/tcg/cpu64.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index 38534dcdd32..60176d08597 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -154,6 +154,7 @@ the following architecture extensions:
- FEAT_VMID16 (16-bit VMID)
- FEAT_WFxT (WFE and WFI instructions with timeout)
- FEAT_XNX (Translation table stage 2 Unprivileged Execute-never)
+- FEAT_XS (XS attribute)
For information on the specifics of these extensions, please refer
to the `Arm Architecture Reference Manual for A-profile architecture
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 2963d7510f3..449cec5a626 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -1163,6 +1163,7 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 2); /* FEAT_BF16, FEAT_EBF16 */
t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */
t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */
+ t = FIELD_DP64(t, ID_AA64ISAR1, XS, 1); /* FEAT_XS */
cpu->isar.id_aa64isar1 = t;
t = cpu->isar.id_aa64isar2;
--
2.34.1
