[PATCH v1 1/1] target/riscv: add VILL field for vtype register macro definition

[Chao Liu]

Signed-off-by: Chao Liu <lc00...@tecorigin.com>
---
 target/riscv/cpu.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 284b112821..fc286484b8 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -170,7 +170,8 @@ FIELD(VTYPE, VSEW, 3, 3)
 FIELD(VTYPE, VTA, 6, 1)
 FIELD(VTYPE, VMA, 7, 1)
 FIELD(VTYPE, VEDIV, 8, 2)
-FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)
+FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 12)
+FIELD(VTYPE, VILL, 63, 1)
 
 typedef struct PMUCTRState {
     /* Current value of a counter */
-- 
2.47.0