Remove disas_fp_int_conv and disas_data_proc_fp as these
were the last insns decoded by those functions.
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
target/arm/tcg/translate-a64.c | 232 ++++++++++-----------------------
target/arm/tcg/a64.decode | 14 ++
2 files changed, 86 insertions(+), 160 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index d260b45ddb..95bb2b1ca9 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8734,175 +8734,87 @@ static bool trans_FJCVTZS(DisasContext *s, arg_FJCVTZS
*a)
return true;
}
-static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
+static bool trans_FMOV_hx(DisasContext *s, arg_rr *a)
{
- /* FMOV: gpr to or from float, double, or top half of quad fp reg,
- * without conversion.
- */
-
- if (itof) {
- TCGv_i64 tcg_rn = cpu_reg(s, rn);
- TCGv_i64 tmp;
-
- switch (type) {
- case 0:
- /* 32 bit */
- tmp = tcg_temp_new_i64();
- tcg_gen_ext32u_i64(tmp, tcg_rn);
- write_fp_dreg(s, rd, tmp);
- break;
- case 1:
- /* 64 bit */
- write_fp_dreg(s, rd, tcg_rn);
- break;
- case 2:
- /* 64 bit to top half. */
- tcg_gen_st_i64(tcg_rn, tcg_env, fp_reg_hi_offset(s, rd));
- clear_vec_high(s, true, rd);
- break;
- case 3:
- /* 16 bit */
- tmp = tcg_temp_new_i64();
- tcg_gen_ext16u_i64(tmp, tcg_rn);
- write_fp_dreg(s, rd, tmp);
- break;
- default:
- g_assert_not_reached();
- }
- } else {
- TCGv_i64 tcg_rd = cpu_reg(s, rd);
-
- switch (type) {
- case 0:
- /* 32 bit */
- tcg_gen_ld32u_i64(tcg_rd, tcg_env, fp_reg_offset(s, rn, MO_32));
- break;
- case 1:
- /* 64 bit */
- tcg_gen_ld_i64(tcg_rd, tcg_env, fp_reg_offset(s, rn, MO_64));
- break;
- case 2:
- /* 64 bits from top half */
- tcg_gen_ld_i64(tcg_rd, tcg_env, fp_reg_hi_offset(s, rn));
- break;
- case 3:
- /* 16 bit */
- tcg_gen_ld16u_i64(tcg_rd, tcg_env, fp_reg_offset(s, rn, MO_16));
- break;
- default:
- g_assert_not_reached();
- }
+ if (!dc_isar_feature(aa64_fp16, s)) {
+ return false;
}
+ if (fp_access_check(s)) {
+ TCGv_i64 tcg_rn = cpu_reg(s, a->rn);
+ TCGv_i64 tmp = tcg_temp_new_i64();
+ tcg_gen_ext16u_i64(tmp, tcg_rn);
+ write_fp_dreg(s, a->rd, tmp);
+ }
+ return true;
}
-/* Floating point <-> integer conversions
- * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
- * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
- * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
- * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
- */
-static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
+static bool trans_FMOV_sw(DisasContext *s, arg_rr *a)
{
- int rd = extract32(insn, 0, 5);
- int rn = extract32(insn, 5, 5);
- int opcode = extract32(insn, 16, 3);
- int rmode = extract32(insn, 19, 2);
- int type = extract32(insn, 22, 2);
- bool sbit = extract32(insn, 29, 1);
- bool sf = extract32(insn, 31, 1);
- bool itof = false;
-
- if (sbit) {
- goto do_unallocated;
- }
-
- switch (opcode) {
- case 2: /* SCVTF */
- case 3: /* UCVTF */
- case 4: /* FCVTAS */
- case 5: /* FCVTAU */
- case 0: /* FCVT[NPMZ]S */
- case 1: /* FCVT[NPMZ]U */
- goto do_unallocated;
-
- default:
- switch (sf << 7 | type << 5 | rmode << 3 | opcode) {
- case 0b01100110: /* FMOV half <-> 32-bit int */
- case 0b01100111:
- case 0b11100110: /* FMOV half <-> 64-bit int */
- case 0b11100111:
- if (!dc_isar_feature(aa64_fp16, s)) {
- goto do_unallocated;
- }
- /* fallthru */
- case 0b00000110: /* FMOV 32-bit */
- case 0b00000111:
- case 0b10100110: /* FMOV 64-bit */
- case 0b10100111:
- case 0b11001110: /* FMOV top half of 128-bit */
- case 0b11001111:
- if (!fp_access_check(s)) {
- return;
- }
- itof = opcode & 1;
- handle_fmov(s, rd, rn, type, itof);
- break;
-
- case 0b00111110: /* FJCVTZS */
- default:
- do_unallocated:
- unallocated_encoding(s);
- return;
- }
- break;
+ if (fp_access_check(s)) {
+ TCGv_i64 tcg_rn = cpu_reg(s, a->rn);
+ TCGv_i64 tmp = tcg_temp_new_i64();
+ tcg_gen_ext32u_i64(tmp, tcg_rn);
+ write_fp_dreg(s, a->rd, tmp);
}
+ return true;
}
-/* FP-specific subcases of table C3-6 (SIMD and FP data processing)
- * 31 30 29 28 25 24 0
- * +---+---+---+---------+-----------------------------+
- * | | 0 | | 1 1 1 1 | |
- * +---+---+---+---------+-----------------------------+
- */
-static void disas_data_proc_fp(DisasContext *s, uint32_t insn)
+static bool trans_FMOV_dx(DisasContext *s, arg_rr *a)
{
- if (extract32(insn, 24, 1)) {
- unallocated_encoding(s); /* in decodetree */
- } else if (extract32(insn, 21, 1) == 0) {
- /* Floating point to fixed point conversions */
- unallocated_encoding(s); /* in decodetree */
- } else {
- switch (extract32(insn, 10, 2)) {
- case 1: /* Floating point conditional compare */
- case 2: /* Floating point data-processing (2 source) */
- case 3: /* Floating point conditional select */
- unallocated_encoding(s); /* in decodetree */
- break;
- case 0:
- switch (ctz32(extract32(insn, 12, 4))) {
- case 0: /* [15:12] == xxx1 */
- /* Floating point immediate */
- unallocated_encoding(s); /* in decodetree */
- break;
- case 1: /* [15:12] == xx10 */
- /* Floating point compare */
- unallocated_encoding(s); /* in decodetree */
- break;
- case 2: /* [15:12] == x100 */
- /* Floating point data-processing (1 source) */
- unallocated_encoding(s); /* in decodetree */
- break;
- case 3: /* [15:12] == 1000 */
- unallocated_encoding(s);
- break;
- default: /* [15:12] == 0000 */
- /* Floating point <-> integer conversions */
- disas_fp_int_conv(s, insn);
- break;
- }
- break;
- }
+ if (fp_access_check(s)) {
+ TCGv_i64 tcg_rn = cpu_reg(s, a->rn);
+ write_fp_dreg(s, a->rd, tcg_rn);
}
+ return true;
+}
+
+static bool trans_FMOV_ux(DisasContext *s, arg_rr *a)
+{
+ if (fp_access_check(s)) {
+ TCGv_i64 tcg_rn = cpu_reg(s, a->rn);
+ tcg_gen_st_i64(tcg_rn, tcg_env, fp_reg_hi_offset(s, a->rd));
+ clear_vec_high(s, true, a->rd);
+ }
+ return true;
+}
+
+static bool trans_FMOV_xh(DisasContext *s, arg_rr *a)
+{
+ if (!dc_isar_feature(aa64_fp16, s)) {
+ return false;
+ }
+ if (fp_access_check(s)) {
+ TCGv_i64 tcg_rd = cpu_reg(s, a->rd);
+ tcg_gen_ld16u_i64(tcg_rd, tcg_env, fp_reg_offset(s, a->rn, MO_16));
+ }
+ return true;
+}
+
+static bool trans_FMOV_ws(DisasContext *s, arg_rr *a)
+{
+ if (fp_access_check(s)) {
+ TCGv_i64 tcg_rd = cpu_reg(s, a->rd);
+ tcg_gen_ld32u_i64(tcg_rd, tcg_env, fp_reg_offset(s, a->rn, MO_32));
+ }
+ return true;
+}
+
+static bool trans_FMOV_xd(DisasContext *s, arg_rr *a)
+{
+ if (fp_access_check(s)) {
+ TCGv_i64 tcg_rd = cpu_reg(s, a->rd);
+ tcg_gen_ld_i64(tcg_rd, tcg_env, fp_reg_offset(s, a->rn, MO_64));
+ }
+ return true;
+}
+
+static bool trans_FMOV_xu(DisasContext *s, arg_rr *a)
+{
+ if (fp_access_check(s)) {
+ TCGv_i64 tcg_rd = cpu_reg(s, a->rd);
+ tcg_gen_ld_i64(tcg_rd, tcg_env, fp_reg_hi_offset(s, a->rn));
+ }
+ return true;
}
/* Common vector code for handling integer to FP conversion */
@@ -10821,7 +10733,7 @@ static void disas_data_proc_simd(DisasContext *s,
uint32_t insn)
static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn)
{
if (extract32(insn, 28, 1) == 1 && extract32(insn, 30, 1) == 0) {
- disas_data_proc_fp(s, insn);
+ unallocated_encoding(s); /* in decodetree */
} else {
/* SIMD, including crypto */
disas_data_proc_simd(s, insn);
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index cd10961618..5b9f7caa7f 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -1365,6 +1365,20 @@ FCVTAU_g . 0011110 .. 100101 000000 ..... .....
@icvt
FJCVTZS 0 0011110 01 111110 000000 ..... ..... @rr
+FMOV_ws 0 0011110 00 100110 000000 ..... ..... @rr
+FMOV_sw 0 0011110 00 100111 000000 ..... ..... @rr
+
+FMOV_xd 1 0011110 01 100110 000000 ..... ..... @rr
+FMOV_dx 1 0011110 01 100111 000000 ..... ..... @rr
+
+# Move to/from upper half of 128-bit
+FMOV_xu 1 0011110 10 101110 000000 ..... ..... @rr
+FMOV_ux 1 0011110 10 101111 000000 ..... ..... @rr
+
+# Half-precision allows both sf=0 and sf=1 with identical results
+FMOV_xh - 0011110 11 100110 000000 ..... ..... @rr
+FMOV_hx - 0011110 11 100111 000000 ..... ..... @rr
+
# Floating-point data processing (1 source)
FMOV_s 00011110 .. 1 000000 10000 ..... ..... @rr_hsd
--
2.43.0
