Based-on: 20241210160452.2427965-1-peter.mayd...@linaro.org
("target/arm: Pull TLBI insns out to their own source file")The FEAT_XS feature was introduced in ARMv8.7: it adds a new memory attribute XS which indicates that a memory access could take longer than usual to complete, and also adds instruction variants for TLBI maintenance and DSB. For QEMU, we don't have any concept of "really slow memory regions", so we don't need to implement the XS attribute to do anything special. So we only need to implement the new TLBI, DSB, etc as doing the same as the non-XS versions. This is a respin of Manos' v1 patchseries. In particular: * patch 1 adds support for the fine-grained-trap handling for the new TLBI NXS insns * patches 2 and 3 implement the actual TLB insns in a different way to v1: we add a new ARM_CP_ADD_TLBI_NXS cpreg type flag which we can mark the existing TLBI insns with; the core cpregs machinery will then autogenerate the TLBI NXS cpreg when FEAT_XS is present. The aim is to avoid having a lot of mostly-duplicate cpreg structs and arrays. * patches 4, 5, 6 have only minor changes from v1 to address issues raised in code review thanks -- PMM Manos Pitsidianakis (3): target/arm: Add decodetree entry for DSB nXS variant target/arm: Enable FEAT_XS for the max cpu tests/tcg/aarch64: add system test for FEAT_XS Peter Maydell (3): target/arm: Implement fine-grained-trap handling for FEAT_XS target/arm: Add ARM_CP_ADD_TLBI_NXS type flag for NXS insns target/arm: Add ARM_CP_ADD_TLBI_NXS type flag to TLBI insns docs/system/arm/emulation.rst | 1 + target/arm/cpregs.h | 80 +++++++----- target/arm/cpu-features.h | 5 + target/arm/tcg/a64.decode | 3 + target/arm/helper.c | 30 ++++- target/arm/tcg/cpu64.c | 1 + target/arm/tcg/op_helper.c | 11 +- target/arm/tcg/tlb-insns.c | 202 ++++++++++++++++++----------- target/arm/tcg/translate-a64.c | 9 ++ tests/tcg/aarch64/system/feat-xs.c | 27 ++++ 10 files changed, 259 insertions(+), 110 deletions(-) create mode 100644 tests/tcg/aarch64/system/feat-xs.c -- 2.34.1
