If an alignment fault occurred and target EL is using AArch32,
then DFSR/IFSR bit LPAE[9] must be set correctly.
Signed-off-by: Sergey Sorokin
---
target-arm/op_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index
Some PL2 related TLBI system registers are missed in AArch32
implementation. The patch fixes it.
Signed-off-by: Sergey Sorokin
---
In the second version of the patch some new system registers
was moved into another groups. Some write functions was
slightly changed.
target-arm/helper.c | 139
11.07.2016, 21:36, "Peter Maydell" :
> On 11 July 2016 at 19:23, Sergey Sorokin wrote:
>> 11.07.2016, 20:39, "Peter Maydell" :
>>>> +
>>>> + CPU_FOREACH(other_cs) {
>>>> + tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMU
11.07.2016, 20:39, "Peter Maydell" :
>> +
>> + CPU_FOREACH(other_cs) {
>> + tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E2, -1);
>> + }
>> +}
>> +
>> static const ARMCPRegInfo cp_reginfo[] = {
>> /* Define the secure and non-secure FCSE identifier CP registers
>> *
ping
http://patchwork.ozlabs.org/patch/639688/
11.07.2016, 05:18, "David Gibson" :
> I'm afraid your mailer has turned this into an unreadable HTML mess.
It was just a ping.
http://patchwork.ozlabs.org/patch/635235/
Â
14.06.2016, 15:26, "Sergey Sorokin" :
There are functions tlb_fill(), cpu_unaligned_access() and
do_unaligned_access() that are called with access type and mmu index
arguments. But these arguments are named 'is_write' and 'is_user' in
I have sentA the fourth version of the patch.
A
A build failure was fixed.
Yes, I thought about it. tcg_canonicalize_memop() is good place too.
But do you think that get_alignment_bits() is not good enough?
23.06.2016, 19:13, "Richard Henderson" :
> On 06/23/2016 07:13 AM, Sergey Sorokin wrote:
>>> I think we ought to check this in tcg-op.c,
Some architectures (e.g. ARMv8) need the address which is aligned
to a size more than the size of the memory access.
To support such check it's enough the current costless alignment
check implementation in QEMU, but we need to support
an alignment size specifying.
Signed-off-by: Sergey So
I have sentA the third version of the patch.
Some architectures (e.g. ARMv8) need the address which is aligned
to a size more than the size of the memory access.
To support such check it's enough the current costless alignment
check implementation in QEMU, but we need to support
an alignment size specifying.
Signed-off-by: Sergey So
A
A
23.06.2016, 17:05, "Richard Henderson" :
On 06/23/2016 03:03 AM, Sergey Sorokin wrote:
A So what's wrong in this part of the patch?
I think I just misread it.
A
It happens :)
A
A
22.06.2016, 18:50, "Richard Henderson" :
So what's wrong in this part of the patch?
22.06.2016, 20:12, "Richard Henderson" :
> On 06/22/2016 09:30 AM, Sergey Sorokin wrote:
>>> diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
>>> index da10052..3dc38fa 100644
>
A
A
22.06.2016, 18:50, "Richard Henderson" :
On 06/22/2016 05:37 AM, Sergey Sorokin wrote:
A +/* Use this mask to check interception with an alignment mask
A + * in a TCG backend.
A + */
A +#define TLB_FLAGS_MASK (TLB_INVALID_MASK | TL
Sorry, I have sent wrong patch.
A
By the way, the second version of the patch was sent already.
I have sentA the second version of the patch.
Some architectures (e.g. ARMv8) need the address which is aligned
to a size more than the size of the memory access.
It's enougth the current costless alignment check implementation in QEMU,
but we need to support the alignment size specifying.
Signed-off-by: Sergey Sorokin
---
include/exe
Some architectures (e.g. ARMv8) need the address which is aligned
to a size more than the size of the memory access.
To support such check it's enough the current costless alignment
check implementation in QEMU, but we need to support
an alignment size specifying.
Signed-off-by: Sergey So
A
A
20.06.2016, 18:45, "Richard Henderson" :
On 06/20/2016 06:56 AM, Sergey Sorokin wrote:
A A /* Flags stored in the low bits of the TLB virtual address.
These are
A - defined so that fast path ram access is all zeros. */
A + * defined so that fas
Some architectures (e.g. ARMv8) need the address which is aligned
to a size more than the size of the memory access.
It's enougth the current costless alignment check implementation in QEMU,
but we need to support the alignment size specifying.
Signed-off-by: Sergey Sorokin
---
include/exe
15.06.2016, 06:03, "David Gibson" :
> On Tue, Jun 14, 2016 at 03:26:17PM +0300, Sergey Sorokin wrote:
>> There are functions tlb_fill(), cpu_unaligned_access() and
>> do_unaligned_access() that are called with access type and mmu index
>> arguments. But these arg
There are functions tlb_fill(), cpu_unaligned_access() and
do_unaligned_access() that are called with access type and mmu index
arguments. But these arguments are named 'is_write' and 'is_user' in their
declarations. The patches fix the arguments to avoid a confusion.
S
Seems arm_cpu_do_unaligned_access() function could use it. It uses
cpu_mmu_index() for now but I think use of mmu_idx is preferred. Anyway it's
the subject for another patch.
13.06.2016, 10:47, "Aurelien Jarno" :
> On 2016-06-10 19:26, Sergey Sorokin wrote:
>&
cpu-common.h is not included in qom/cpu.h
what do you think? Should it be included? Or may be MMUAccessType should be
just moved into another header. For example into exec/memattrs.h
10.06.2016, 19:44, "Peter Maydell" :
> On 10 June 2016 at 17:42, Sergey Sorokin wrote:
>>
What if I combine both patches into single one?
10.06.2016, 19:33, "Peter Maydell" :
> On 10 June 2016 at 17:26, Sergey Sorokin wrote:
>> There are functions cpu_unaligned_access() and do_unaligned_access() that
>> are called with access type and mmu index argum
I agree
10.06.2016, 19:33, "Peter Maydell" :
> On 10 June 2016 at 17:26, Sergey Sorokin wrote:
>> There are functions cpu_unaligned_access() and do_unaligned_access() that
>> are called with access type and mmu index arguments. But these arguments
>> are na
The function tlb_fill() is called with access type argument which is named
'is_write' in its declaration. The patch fixes the argument name
to avoid a confusion.
Signed-off-by: Sergey Sorokin
---
include/exec/exec-all.h | 2 +-
target-alpha/mem_helper.c | 4 ++--
There are functions cpu_unaligned_access() and do_unaligned_access() that
are called with access type and mmu index arguments. But these arguments
are named 'is_write' and 'is_user' in their declarations.
The patch fixes the names to avoid a confusion.
Signed-off-by: Sergey S
There are functions tlb_fill(), cpu_unaligned_access() and
do_unaligned_access() that are called with access type and mmu index
arguments. But these arguments are named 'is_write' and 'is_user' in their
declarations. The patches fix the names to avoid a confusion.
Serge
Address size is 40-bit for the AArch32 stage 2 translation,
and t0sz can be negative (from -8 to 7),
so we need to adjust it to use the existing TTBR selecting logic.
Signed-off-by: Sergey Sorokin
---
target-arm/helper.c | 38 ++
1 file changed, 22 insertions
26.04.2016, 19:35, "Tom Hanson" :On 03/21/2016 09:56 AM, Sergey Sorokin wrote: 17.03.2016, 18:24, "Peter Maydell" <peter.mayd...@linaro.org>: On 17 March 2016 at 15:21, Sergey Sorokin <afaral...@yandex.ru> wrote:17.03.2016, 14:40, "Peter Maydell"
There is a duplicating code in AArch32 exception return implementation.
The patch rearranges the code to avoid this.
Signed-off-by: Sergey Sorokin
---
target-arm/translate.c | 36 +---
1 file changed, 21 insertions(+), 15 deletions(-)
diff --git a/target-arm
There is a duplicating code in AArch32 exception return implementation.
Also there is a missed exception return on AArch32 instruction ADDS r15.
The patches rearrange the code and fix these issues.
Sergey Sorokin (2):
target-arm: Unify AArch32 exception return generating functions
target-arm
In AArch32 instruction ADDS r15, ... is used for exception return.
Signed-off-by: Sergey Sorokin
---
target-arm/translate.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 68671b7..3e64ba9 100644
--- a
As described in AArch32.CheckS2Permission an instruction fetch fails if
XN bit is set or there is no read permission for the address.
Signed-off-by: Sergey Sorokin
---
target-arm/helper.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm
o pseudo-code.
The patch fixes both cases.
Signed-off-by: Sergey Sorokin
---
Fixed a comment before the calculation of 'descaddrmask' value.
target-arm/helper.c | 29 +++--
1 file changed, 11 insertions(+), 18 deletions(-)
diff --git a/target-arm/helper.c b/ta
17.03.2016, 18:24, "Peter Maydell" :
> On 17 March 2016 at 15:21, Sergey Sorokin wrote:
>> 17.03.2016, 14:40, "Peter Maydell" :
>>> On 13 March 2016 at 18:28, Sergey Sorokin wrote:
>>>>> If you want to implement the AddressSize checks
17.03.2016, 14:40, "Peter Maydell" :
> On 13 March 2016 at 18:28, Sergey Sorokin wrote:
>>> If you want to implement the AddressSize checks that's fine,
>>> but otherwise please leave this bit of the code alone.
>>
>> You said me that my code is no
12.03.2016, 03:18, "Peter Maydell" :
>On 12 March 2016 at 06:44, Sergey Sorokin wrote:
>> 11.03.2016, 11:41, "Peter Maydell" :
>>>On 4 March 2016 at 23:04, Sergey Sorokin wrote:
>>>> There is a bug in ARM address translation regime with a long
11.03.2016, 11:41, "Peter Maydell" :
>On 4 March 2016 at 23:04, Sergey Sorokin wrote:
>> There is a bug in ARM address translation regime with a long-descriptor
>> format. On the descriptor reading its address is formed from an index
>> which is a part of the
Qemu reports translation fault on 1st level instead of 0th level in case of
AArch64 address translation if the translation table walk is disabled or
the address is in the gap between the two regions.
Signed-off-by: Sergey Sorokin
---
In the second version of the patch the code was rearranged
to
o pseudo-code.
The patch fixes both cases.
Signed-off-by: Sergey Sorokin
---
target-arm/helper.c | 29 ++---
1 file changed, 10 insertions(+), 19 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index dec8e8b..b5f289c 100644
--- a/target-arm/help
03.03.2016, 19:54, "Peter Maydell" :
> On 3 March 2016 at 16:37, Sergey Fedorov wrote:
>> On 03.03.2016 17:55, Peter Maydell wrote:
>>> Yes, this patch is definitely fixing a bug; I'm just mentioning that other
>>> code path because it seems to be the result of previously fixing the bug
>
Qemu reports translation fault on 1st level instead of 0th level in case of
AArch64 address translation if the translation table walk is disabled or
the address is in the gap between the two regions.
Signed-off-by: Sergey Sorokin
---
target-arm/helper.c | 1 +
1 file changed, 1 insertion
That is ok.
06.10.2015, 00:55, "Peter Maydell" :
> On 2 October 2015 at 14:21, Sergey Sorokin wrote:
>> It is incorrect to call arm_el_is_aa64() function for unimplemented EL.
>> This patch fixes several attempts to do so.
>>
>> Signed-off-by: Sergey Sorok
It is incorrect to call arm_el_is_aa64() function for unimplemented EL.
This patch fixes several attempts to do so.
Signed-off-by: Sergey Sorokin
---
target-arm/cpu.h| 8 +---
target-arm/helper.c | 15 +--
2 files changed, 18 insertions(+), 5 deletions(-)
diff --git a
he TB
after ISB instruction on the code translation.
Also this TB break is necessary to take any pending interrupts immediately
according to ARMv8 ARM D1.14.4.
Signed-off-by: Sergey Sorokin
---
Changes since previous version:
* ARMv6 ISB was also fixed.
* Second reason for TB breaking was mention
Oh, sorry, I forgot about this. A lot of work now.
I'll send the patch.
01.10.2015, 15:12, "Peter Maydell" :
> On 11 September 2015 at 16:55, Sergey Sorokin wrote:
>> 11.09.2015, 18:44, "Peter Maydell" :
>>> On 9 September 2015 at 17:01, Sergey Soro
11.09.2015, 18:44, "Peter Maydell" :
> On 9 September 2015 at 17:01, Sergey Sorokin wrote:
>> If any store instruction writes the code inside the same TB
>> after this store insn, the execution of the TB must be stopped
>> to execute new code correctly.
&
he TB
after ISB instruction on the code translation.
Also this TB break is necessary to take any pending interrupts immediately
according to ARMv8 ARM D1.14.4.
Signed-off-by: Sergey Sorokin
---
Changes since previous version:
* ARMv6 ISB was also fixed.
* Second reason for TB breaking was mention
08.09.2015, 16:44, "Peter Maydell" :
>On 2 September 2015 at 16:39, Sergey Sorokin wrote:
>> Function arm_el_is_aa64() was fixed to support EL2 and EL3.
>> It is needed for a future support of EL2 and/or EL3,
>> and 32 bit EL1/EL2 support for ARMv8 cpu.
>> AR
08.09.2015, 16:52, "Peter Maydell" :
> On 2 September 2015 at 16:39, Sergey Sorokin wrote:
>> If EL3 is not supported in current configuration,
>> we should not try to get EL3 bitness.
>>
>> Signed-off-by: Sergey Sorokin
>> ---
>> targ
There is an error in arm_excp_unmasked() function:
bitwise operator & is used with integer and bool operands
causing an incorrect zeroed result.
The patch fixes it.
Signed-off-by: Sergey Sorokin
---
target-arm/cpu.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --g
was
slightly changed to check it.
Signed-off-by: Sergey Sorokin
---
Changes since previous version:
* Some typos was fixed.
* Extended comments was added.
* The initial patch was divided in two parts.
* The erroneous changes in arm_excp_unmasked() function was fixed.
hw/arm/boot.c| 4
If EL3 is not supported in current configuration,
we should not try to get EL3 bitness.
Signed-off-by: Sergey Sorokin
---
target-arm/translate-a64.c | 6 +-
target-arm/translate.c | 6 +-
target-arm/translate.h | 7 +--
3 files changed, 15 insertions(+), 4 deletions(-)
diff
was
slightly changed to check it.
Signed-off-by: Sergey Sorokin
Sergey Sorokin (2):
target-arm: Fix default_exception_el() function for the case when EL3
is not supported
target-arm: Fix arm_el_is_aa64() function to support EL2 and EL3
hw/arm/boot.c | 4
target-arm
he TB
after ISB instruction on the code translation.
Signed-off-by: Sergey Sorokin
---
In the first version of the patch the TB was broken after IC invalidation
instead of ISB.
target-arm/translate-a64.c | 7 ++-
target-arm/translate.c | 14 --
2 files changed, 18 insertions(
I did so. As I see, the longest line in the message is 78 chars. How short
should it be in the patches?
01.09.2015, 19:57, "Peter Maydell" :
> On 28 August 2015 at 22:14, Sergey Sorokin wrote:
>> There is an error in functions aarch64_sync_32_to_64() and
>> aar
01.09.2015, 19:26, "Peter Maydell" :
> On 17 July 2015 at 17:01, Sergey Sorokin wrote:
>> Function arm_el_is_aa64() was fixed to support EL2 and EL3.
>> It is needed for a future support of EL2 and/or EL3,
>> and 32 bit EL1 support for ARMv8 cpu.
>> AR
There is an error in functions aarch64_sync_32_to_64() and
aarch64_sync_64_to_32() with mapping of registers between AArch32 and AArch64.
The patch fixes it according to ARM ARM D1.20.1 (table D1-77).
Signed-off-by: Sergey Sorokin
---
target-arm/helper.c | 64
27.08.2015, 19:54, "Peter Maydell" :
> On 26 August 2015 at 12:36, Sergey Sorokin wrote:
>> If any store instruction writes the code inside the same TB
>> after this store insn, the execution of the TB must be stopped
>> to execute new code correctly.
>>
17.07.2015, 19:28, "Peter Maydell" :
>On 17 July 2015 at 17:01, Sergey Sorokin wrote:
>> Function arm_el_is_aa64() was fixed to support EL2 and EL3.
>> It is needed for a future support of EL2 and/or EL3,
>> and 32 bit EL1 support for ARMv8 cpu.
>> ARM_FEATUR
HCR_EL2.RW, SCR_EL3.RW and SCR_EL3.NS bits.
If EL2 or EL3 is not permitted by the appropriate ARM_FEATURE flag,
then the function arm_el_is_aa64() aborts on the attempt to get
the bittness of this EL.
Signed-off-by: Sergey Sorokin
---
hw/arm/boot.c | 3 +++
target-arm/cpu.c
64 matches
Mail list logo
