11.07.2016, 21:36, "Peter Maydell" <[email protected]>: > On 11 July 2016 at 19:23, Sergey Sorokin <[email protected]> wrote: >> 11.07.2016, 20:39, "Peter Maydell" <[email protected]>: >>>> + >>>> + CPU_FOREACH(other_cs) { >>>> + tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E2, -1); >>>> + } >>>> +} >>>> + >>>> static const ARMCPRegInfo cp_reginfo[] = { >>>> /* Define the secure and non-secure FCSE identifier CP registers >>>> * separately because there is no secure bank in V8 (no _EL3). This >>>> allows >>>> @@ -1238,6 +1343,14 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { >>>> .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write >>>> }, >>>> { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, >>>> .opc2 = 3, >>>> .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write >>>> }, >>>> + { .name = "TLBIALLNSNH", >>>> + .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, >>>> + .type = ARM_CP_NO_RAW, .access = PL2_W, >>>> + .writefn = tlbiall_nsnh_write }, >>>> + { .name = "TLBIALLNSNHIS", >>>> + .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, >>>> + .type = ARM_CP_NO_RAW, .access = PL2_W, >>>> + .writefn = tlbiall_nsnh_is_write }, >>> >>> These don't exist on v7 unless the virtualization extensions are present >>> (though they do exist on v8 without EL3). >> >> So I should check arm_feature(env, ARM_FEATURE_EL2) to add these registers, >> e.g. by moving them to el2_cp_reginfo, right? > > That would make them incorrectly not exist for v8-without-EL3, I think. > If there isn't a suitable reginfo array for this case, you might need > to either list them in two arrays or add a new array. > > thanks > -- PMM
Table G4-25 Effect of the TLB maintenance instructions says: b. Available only in an implementation that includes EL2. So seems they should be in el2_cp_reginfo which is exist regardless EL3 enabled. And also I need to fix tlbiall_nsnh_[is_]write functions accordingly.
