Does this have any implications when probing with the 'none' machine?
>>>
>>> I'm not sure. In your case, I guess the cpu bit would still show up
>>> as before, so it would tell you base feature availability, but not
>>> whether you can use the new configuration option.
>>>
>>> Since the HTL
Bug reference: https://bugs.launchpad.net/qemu/+bug/1885175
It is possible to hit this assertion on rhel7 guests if iommu is
properly enabled.
Signed-off-by: Eugenio Pérez
---
memory.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/memory.c b/memory.c
index 2f15a4b250..7f789710d2 100644
-
> -Original Message-
> From: Alistair Francis
> Sent: 26 June 2020 00:20
> To: Anup Patel
> Cc: Anup Patel ; Peter Maydell
> ; Palmer Dabbelt ;
> Alistair Francis ; Sagar Karandikar
> ; Atish Patra ; open
> list:RISC-V ; qemu-devel@nongnu.org
> Developers
> Subject: Re: [PATCH v6 5/5]
From: Gustavo Romero
This commit fixes typos in spapr_vio_reg_to_irq() comments and a macro
indentation.
Signed-off-by: Gustavo Romero
Message-Id: <1590710681-12873-1-git-send-email-grom...@linux.ibm.com>
Acked-by: Cédric Le Goater
Signed-off-by: David Gibson
---
hw/ppc/spapr_vio.c |
I am able to hit this assertion when a Red Hat 7 guest virtio_net device
raises an "Invalidation" of all the TLB entries. This happens in the
guest's startup if 'intel_iommu=on' argument is passed to the guest
kernel and right IOMMU/ATS devices are declared in qemu's command line.
Command line:
/h
The following changes since commit 63d211993b73ca9ac2bc618afeb61a698e9f5198:
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
(2020-06-25 16:52:42 +0100)
are available in the Git repository at:
git://github.com/dgibson/qemu.git tags/ppc-for-5.1-20200626
for you to
From: Cédric Le Goater
It is not part of Power ISA Version 3.1.
Signed-off-by: Cédric Le Goater
Message-Id: <20200623154534.266065-1-...@kaod.org>
Signed-off-by: David Gibson
---
target/ppc/translate_init.inc.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/target/ppc/translate_init.
From: Greg Kurz
We obviously only want to print a warning in these cases, but this is done
in a rather convoluted manner. Just use warn_report() instead.
Signed-off-by: Greg Kurz
Message-Id: <159188281098.70166.18387926536399257573.st...@bahia.lan>
Reviewed-by: Vladimir Sementsov-Ogievskiy
Rev
From: Greg Kurz
The device introspect test in qtest emits some warnings with the
the pnv machine types during the "nodefaults" phase:
TEST check-qtest-ppc64: tests/qtest/device-introspect-test
qemu-system-ppc64: warning: machine has no BMC device. Use '-device
ipmi-bmc-sim,id=bmc0 -device isa-ip
Vladimir Sementsov-Ogievskiy writes:
> 24.06.2020 19:43, Markus Armbruster wrote:
>> Convert
>>
>> foo(..., &err);
>> if (err) {
>> ...
>> }
>>
>> to
>>
>> if (!foo(..., &err)) {
>> ...
>> }
>>
>> for qdev_realize(), qdev_realize_and_unref(), qbus_realiz
Sai Pavan Boddu writes:
> Hi Markus,
>
>> -Original Message-
>> From: Markus Armbruster
>> Sent: Thursday, June 25, 2020 1:42 PM
>> To: Sai Pavan Boddu
>> Cc: Gerd Hoffmann ; Peter Maydell
>> ; Thomas Huth ; Eduardo
>> Habkost ; qemu-devel@nongnu.org; Alistair Francis
>> ; 'Marc-André L
Hi!
On 25/06/2020 23.30, David CARLIER wrote:
From 78706a28c6aa8b5e522b5781588b38961d79d6f6 Mon Sep 17 00:00:00 2001
From: David Carlier
Date: Thu, 25 Jun 2020 19:32:42 +
Subject: [PATCH] build: haiku system build fix
The above header lines should not be part of the e-mail body (otherwi
On Jun 25 15:57, Andrzej Jakowski wrote:
> On 6/25/20 4:13 AM, Klaus Jensen wrote:
> >
> > Come to think of it, the above might not even be sufficient since if just
> > one
> > of the nvme_addr_is_cmb checks fails, we end up issuing an invalid
> > pci_dma_read. But I think that it will error out
Philippe Mathieu-Daudé writes:
> On 6/25/20 10:12 AM, Philippe Mathieu-Daudé wrote:
>> On 6/25/20 8:37 AM, Markus Armbruster wrote:
>>> Cédric Le Goater writes:
>>>
On 6/22/20 10:31 AM, Philippe Mathieu-Daudé wrote:
> On 6/22/20 8:27 AM, Cédric Le Goater wrote:
>> On 6/21/20 12:58 A
On Thu, Jun 25, 2020 at 09:06:05AM +0200, David Hildenbrand wrote:
> >> Still unsure how to bring this new machine property and the cpu feature
> >> together. Would be great to have the same interface everywhere, but
> >> having two distinct command line objects depend on each other sucks.
> >
> >
Patchew URL:
https://patchew.org/QEMU/20200626033144.790098-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH v9 00/46] target/arm: Implement ARMv8.5-MemTag, system mode
Type: series
Message-id: 202
Patchew URL:
https://patchew.org/QEMU/20200626033144.790098-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH v9 00/46] target/arm: Implement ARMv8.5-MemTag, system mode
Type: series
Message-id: 202
Patchew URL:
https://patchew.org/QEMU/20200626033144.790098-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH v9 00/46] target/arm: Implement ARMv8.5-MemTag, system mode
Type: series
Message-id: 202
On Thu, Jun 25, 2020 at 08:53:54PM -0700, Richard Henderson wrote:
> On 6/25/20 2:15 PM, Lijun Pan wrote:
> >
> >
> >> On Jun 25, 2020, at 1:37 PM, Richard Henderson
> >> wrote:
> >>
> >> On 6/25/20 10:00 AM, Lijun Pan wrote:
> >>> +#define VDIV_MOD_DO(name, op, element, sign, bit)
On 6/25/20 2:12 PM, Lijun Pan wrote:
> Do you mean not submiting the second patch until all the instructions are
> enabled in the future?
Well, I mean not *merging* the second patch until all of the instructions are
enabled.
r~
We now implement all of the components of MTE, without actually
supporting any tagged memory. All MTE instructions will work,
trivially, so we can enable support.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v6: Delay user-only cpu reset bits to the user-only patch set.
v9: A
Look up the physical address for the given virtual address,
convert that to a tag physical address, and finally return
the host address that backs it.
Signed-off-by: Richard Henderson
---
target/arm/mte_helper.c | 131
1 file changed, 131 insertions(+)
d
This "bit" is a particular value of the page's MemAttr.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v6: Test HCR_EL2.{DC,DCT}; test Stage2 attributes.
v8: Fill in cacheattrs for S1 disabled; retain tagging when
combining attributes; set mte_tagging in arm_cpu_tlb_fill.
--
D1.10 specifies that exception handlers begin with tag checks overridden.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Only set if MTE feature present.
---
target/arm/helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
There are a number of paths by which the TBI is still intact
for user-only in the SVE helpers.
Because we currently always set TBI for user-only, we do not
need to pass down the actual TBI setting from above, and we
can remove the top byte in the inner-most primitives, so that
none are forgotten.
On 6/25/20 2:15 PM, Lijun Pan wrote:
>
>
>> On Jun 25, 2020, at 1:37 PM, Richard Henderson
>> wrote:
>>
>> On 6/25/20 10:00 AM, Lijun Pan wrote:
>>> +#define VDIV_MOD_DO(name, op, element, sign, bit) \
>>> +void helper_v##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
We still need to handle tbi for user-only when mte is inactive.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.h | 1 +
target/arm/translate-a64.c | 2 +-
target/arm/translate-sve.c | 6 --
3 files changed, 6 insertions(+), 3 deletions(-)
diff --gi
Introduce an lvalue macro to wrap target_tlb_bit0.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 13 +
target/arm/helper.c| 2 +-
target/arm/translate-a64.c | 2 +-
3 files changed, 15 insertions(+), 2 deletions(-)
diff --git
> On Jun 23, 2020, at 5:27 AM, Stefan Hajnoczi wrote:
>
> On Thu, Jun 18, 2020 at 02:38:04PM -0700, John G Johnson wrote:
>>> On Jun 15, 2020, at 3:49 AM, Stefan Hajnoczi wrote:
>>> An issue with file descriptor passing is that it's hard to revoke access
>>> once the file descriptor has been
The mte-v4 linux arm kernel development branch requires these tags.
It is still an open question as to whether they will be required
for the final commit.
Signed-off-by: Richard Henderson
---
v9: Split from patch creating the tag memory; sort to the end
since it's not yet certain that it's a
Move the variable declarations to the top of the function,
but do not create a new label before sve_access_check.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v8: Split out from previous patch (pmm).
---
target/arm/translate-sve.c | 12 +++-
1 file changed, 7 insertio
On 6/25/20 2:13 PM, Lijun Pan wrote:
>>> case INDEX_op_mul_vec:
>>> - tcg_debug_assert(vece == MO_32 && have_isa_2_07);
>>> - insn = VMULUWM;
>>> + tcg_debug_assert((vece == MO_32 && have_isa_2_07) ||
>>> + (vece == MO_64 && have_isa_3_10));
>>> +
On 6/25/20 8:30 PM, Richard Henderson wrote:
> Version 9 incorporates some review:
>
> * Adjust some commentary.
> * Added an assert for tbi in aarch64_tr_init_disas_context
> * Split arm,armv8.5-memtag to a new, final, patch. We might
> just leave this one out of qemu mainline until th
We need to check the memattr of a page in order to determine
whether it is Tagged for MTE. Between Stage1 and Stage2,
this becomes simpler if we always collect this data, instead
of occasionally being presented with NULL.
Use the nonnull attribute to allow the compiler to check that
all pointer a
Fill out the stub that was added earlier.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v7: Fix page crossing test (szabolcs nagy).
---
target/arm/internals.h | 2 +
target/arm/mte_helper.c | 165 +++-
2 files changed, 166 insertions(+),
This is DC GVA and DC GZVA, and the tag check for DC ZVA.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Use allocation_tag_mem + memset.
v3: Require pre-cleaned addresses.
v6: Move DCZ block size assert to cpu realize.
Perform a tag check for DC ZVA.
---
target/arm/cpu
Fill out the stub that was added earlier.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v8: Remove ra argument to mte_probe1 (pmm).
---
target/arm/internals.h | 48 +++
target/arm/mte_helper.c | 132 +++-
2 files changed, 179 i
Because the elements are sequential, we can eliminate many tests all
at once when the tag hits TCMA, or if the page(s) are not Tagged.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 47 +++
target/arm/sve_helper.c| 95 -
Because the elements are sequential, we can eliminate many tests all
at once when the tag hits TCMA, or if the page(s) are not Tagged.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 98
target/arm/sve_helper.c| 99
Because the elements are sequential, we can eliminate many tests all
at once when the tag hits TCMA, or if the page(s) are not Tagged.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 1 +
target/arm/helper-sve.h| 58 ++
target/arm/inte
Replace existing uses of check_data_tbi in translate-a64.c that
perform multiple logical memory access. Leave the helper blank
for now to reduce the patch size.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper-a64.h| 1 +
target/arm/translate-a64.h | 2 ++
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-sve.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 4a613ca689..4fa521989d 100644
--- a/target/arm/translate-sve.c
+++ b/
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v8: Drop the out-of-line helper (pmm).
---
target/arm/translate-sve.c | 61 +-
1 file changed, 33 insertions(+), 28 deletions(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve
We will shortly need this in mte_helper.c as well.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 36
target/arm/helper.c| 36
2 files changed, 36 insertions(+), 36 deletions(
We will shortly need this in mte_helper.c as well.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 9 +
target/arm/helper.c| 9 -
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/inter
Like the regular data cache flushes, these are nops within qemu.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v6: Split out and handle el0 cache ops properly.
---
target/arm/helper.c | 65 +
1 file changed, 65 insertions(+)
diff --
Signed-off-by: Richard Henderson
---
v5: Assign cs->num_ases to the final value first.
Downgrade to ID_AA64PFR1.MTE=1 if tag memory is not available.
v6: Add secure tag memory for EL3.
v8: Add arm,armv8.5-memtag.
v9: Split arm,armv8.5-memtag to another patch;
adjust how address spaces are
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v3: Require pre-cleaned addresses.
v6: Check full mte enabled. Reorg the helpers.
---
target/arm/helper-a64.h| 3 ++
target/arm/translate.h | 2 +
target/arm/mte_helper.c| 84 ++
ta
Use a special helper for DC_ZVA, rather than the more
general mte_checkN.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper-a64.h| 1 +
target/arm/mte_helper.c| 106 +
target/arm/translate-a64.c | 16 +-
3 files
Because the elements are non-sequential, we cannot eliminate many
tests straight away like we can for sequential operations. But
we often have the PTE details handy, so we can test for Tagged.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 285
Use the same code as system mode, so that we generate the same
exception + syndrome for the unaligned access.
For the moment, if MTE is enabled so that this path is reachable,
this would generate a SIGSEGV in the user-only cpu_loop. Decoding
the syndrome to produce the proper SIGBUS will be done
We can simplify our DC_ZVA if we recognize that the largest BS
that we actually use in system mode is 64. Let us just assert
that it fits within TARGET_PAGE_SIZE.
For DC_GVA and STZGM, we want to be able to write whole bytes
of tag memory, so assert that BS is >= 2 * TAG_GRANULE, or 32.
Reviewed
Replace existing uses of check_data_tbi in translate-a64.c that
perform a single logical memory access. Leave the helper blank
for now to reduce the patch size.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper-a64.h| 1 +
target/arm/internals.h | 8
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v6: Inline the operation.
---
target/arm/translate-a64.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 2ec02c8a5f..ee9dfa8e43 100644
--- a/target/a
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v3: Handle atomicity, require pre-cleaned address.
v6: Fix constant offset shift, non-checked address, use pre-computed ata.
---
target/arm/translate-a64.c | 29 ++---
1 file changed, 26 insertions(+), 3 dele
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Shift offset in translate; use extract32.
v6: Implement inline for !ATA.
v8: Use separate decode function.
---
target/arm/helper-a64.h| 1 +
target/arm/internals.h | 9 +++
target/arm/mte_helper.c| 10
Now that we know that the operation is on a single page,
we need not loop over pages while probing.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper-a64.c | 94 +++--
1 file changed, 25 insertions(+), 69 deletions(-)
diff --g
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v8: Drop the out-of-line helper (pmm).
---
target/arm/translate-sve.c | 61 +-
1 file changed, 33 insertions(+), 28 deletions(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Fix extraction length.
---
target/arm/translate-a64.c | 24 ++--
1 file changed, 22 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index ee9dfa8e43..abbcdb
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Split out allocation_tag_mem. Handle atomicity of stores.
v3: Add X[t] input to these insns; require pre-cleaned addresses.
v5: Fix !32-byte aligned operation of st2g.
v6: Fix op2 extract, stg pre/post-index, stores vs sp, comme
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v2: Update to 00eac5.
Merge choose_random_nonexcluded_tag into helper_irg since
that pseudo function no longer exists separately.
v6: Remove obsolete logical/physical tag distinction;
implement inline for !ATA.
---
targe
This is TFSRE0_EL1, TFSR_EL1, TFSR_EL2, TFSR_EL3,
RGSR_EL1, GCR_EL1, GMID_EL1, and PSTATE.TCO.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v3: Add GMID; add access_mte.
v4: Define only TCO at mte_insn_reg.
v6: Define RAZ/WI version of TCO at mte_insn_reg;
honor TID5 for G
Cache the composite ATA setting.
Cache when MTE is fully enabled, i.e. access to tags are enabled
and tag checks affect the PE. Do this for both the normal context
and the UNPRIV context.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v3: Remove stub helper_mte_check; moved to
This does not attempt to rectify all of the res0 bits, but does
clear the mte bits when not enabled. Since there is no high-part
mapping of SCTLR, aa32 mode cannot write to these bits.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 23 +---
Add an option that writes back the PC, like DISAS_UPDATE_EXIT,
but does not exit back to the main loop.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate.h | 2 ++
target/arm/translate-a64.c | 3 +++
target/arm/translate.c | 4
3 files changed, 9
Emphasize that the is_jmp option exits to the main loop.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate.h | 14 --
target/arm/translate-a64.c | 8
target/arm/translate-vfp.inc.c | 4 ++--
target/arm/translate.c | 1
The current Arm ARM has adjusted the official decode of
"Add/subtract (immediate)" so that the shift field is only bit 22,
and bit 23 is part of the op1 field of the parent category
"Data processing - immediate".
Reviewed-by: Peter Maydell
Suggested-by: Peter Maydell
Signed-off-by: Richard Hende
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index cf66b8c7fb..ff70115801 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3814,6 +3814,16 @@ static inl
Protect reads of aa64 id registers with ARM_CP_STATE_AA64.
Use this as a simpler test than arm_el_is_aa64, since EL3
cannot change mode.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
dif
Version 9 incorporates some review:
* Adjust some commentary.
* Added an assert for tbi in aarch64_tr_init_disas_context
* Split arm,armv8.5-memtag to a new, final, patch. We might
just leave this one out of qemu mainline until the kernel
patch set that requires it gets merged.
r~
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v8: Include HCR_DCT.
---
target/arm/helper.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 8a0fb01581..d6c326b58e 100644
--- a/target/arm/helper.c
Patchew URL:
https://patchew.org/QEMU/alpine.deb.2.21.2006252355430.3...@digraph.polyomino.org.uk/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH 0/2] target/i386: SSE floating-point fixes
Type: series
Message-id: alpine.deb.2.
Hi everyone,
I am pleased to announce that the QEMU v4.2.1 stable release is now
available:
You can grab the tarball from our download page here:
https://www.qemu.org/download/#source
v4.2.1 is now tagged in the official qemu.git repository,
and the stable-4.2 branch has been updated accordin
Greetings,
I had been trying to install qemu from the source. I tried both the methods
given on https://www.qemu.org/downloads/#source
And also as given on https://wiki.qemu.org/Hosts/Linux
But in all cases ,I am getting same error every time. Screenshot attached.
Request you all to kindly look in
OpenSBI is the default firmware in Qemu and has various firmware loading
options. Currently, qemu loader uses fw_jump which has a compile time
pre-defined address where fdt & kernel image must reside. This puts a
constraint on image size of the Linux kernel depending on the fdt location
and availab
Currently, all riscv machines except sifive_u have identical reset vector
code implementations with memory addresses being different for all machines.
They can be easily combined into a single function in common code.
Move it to common function and let all the machines use the common function.
Si
Currently, the fdt is copied to the ROM after the reset vector. The firmware
has to copy it to DRAM. Instead of this, directly copy the device tree to a
pre-computed dram address. The device tree load address should be as far as
possible from kernel and initrd images. That's why it is kept at the e
This series adds support OpenSBI dynamic firmware support to Qemu.
Qemu loader passes the information about the DT and next stage (i.e. kernel
or U-boot) via "a2" register. It allows the user to build bigger OS images
without worrying about overwriting DT. It also unifies the reset vector code
in r
The SSE instruction implementations all fail to raise the expected
IEEE floating-point exceptions because they do nothing to convert the
exception state from the softfloat machinery into the exception flags
in MXCSR.
Fix this by adding such conversions. Unlike for x87, emulated SSE
floating-point
The code to set floating-point state when MXCSR changes calls
set_flush_to_zero on &env->fp_status, so affecting the x87
floating-point state rather than the SSE state. Fix to call it for
&env->sse_status instead.
Signed-off-by: Joseph Myers
---
target/i386/fpu_helper.c | 2 +-
1 file changed,
Fix some issues relating to SSE floating-point emulation. The first
patch fixes a problem with the handling of the FTZ bit that was found
through the testcase written for the second patch. Rather than
writing a separate standalone test for that bug, it seemed sufficient
for the testcase in the se
On 6/25/20 1:32 PM, Igor Mammedov wrote:
> On Thu, 25 Jun 2020 11:41:25 -0500
> Babu Moger wrote:
>
>> Igor,
>>
>>> -Original Message-
>>> From: Igor Mammedov
>>> Sent: Thursday, June 25, 2020 10:19 AM
>>> To: Moger, Babu
>>> Cc: ehabk...@redhat.com; m...@redhat.com; qemu-devel@nongn
'virtm' is a hardware target that is designed to be used for compiler
and library testing on Cortex-M processors. It supports all cortex-m
processors and includes sufficient memory to run even large test
cases.
Signed-off-by: Keith Packard
---
MAINTAINERS | 9 +++-
hw/arm/Makefile.obj
On 6/25/20 4:13 AM, Klaus Jensen wrote:
> On Jun 22 11:25, Andrzej Jakowski wrote:
>> So far it was not possible to have CMB and PMR emulated on the same
>> device, because BAR2 was used exclusively either of PMR or CMB. This
>> patch places CMB at BAR4 offset so it not conflicts with MSI-X vectors
On 6/18/20 3:27 AM, Auger Eric wrote:
I have to defer this series since there are some things that don't work
on the Linux level with IRQ 13 (edge) while they do work fine on the old
IRQ 5 (festeoi). I know which changes to make to Linux so that it works
on IRQ 13 as well, but I am not sure wh
On 6/25/20 10:09 AM, Peter Maydell wrote:
>>> Comment says we're checking a memory attribute, but the code
>>> is checking for TLB_MMIO, which isn't the same thing.
>>
>> Comment is not trying to allude to Normal vs Device, but "ram" vs "mmio" in
>> the
>> qemu sense.
>
> Oh, I see: maybe "if not
Injecting external data abort through KVM might trigger
an issue on kernels that do not get updated to include the KVM fix.
For those and aarch32 guests, the injected abort gets misconfigured
to be an implementation defined exception. This leads to the guest
repeatedly re-running the faulting instr
On ARMv7 & ARMv8 some load/store instructions might trigger a data abort
exception with no valid ISS info to be decoded. The lack of decode info
makes it at least tricky to emulate those instruction which is one of the
(many) reasons why KVM will not even try to do so.
Add support for handling tho
Some of the ARMv7 & ARMv8 load/store instructions might trigger a data abort
exception with no valid ISS info to be decoded. The lack of decode info
makes it at least tricky to emulate the instruction which is one of the
(many) reasons why KVM will not even try to do so.
So far, if a guest made an
Your pipeline has failed.
Project: QEMU ( https://gitlab.com/qemu-project/qemu )
Branch: master ( https://gitlab.com/qemu-project/qemu/-/commits/master )
Commit: 63d21199 (
https://gitlab.com/qemu-project/qemu/-/commit/63d211993b73ca9ac2bc618afeb61a698e9f5198
)
Commit Message: Merge remote-tr
>From 78706a28c6aa8b5e522b5781588b38961d79d6f6 Mon Sep 17 00:00:00 2001
From: David Carlier
Date: Thu, 25 Jun 2020 19:32:42 +
Subject: [PATCH] build: haiku system build fix
Most of missing features resides in the bsd library.
Also defining constant equivalence.
Signed-off-by: David Carlier
Patchew URL:
https://patchew.org/QEMU/CA+XhMqy_bAnWm3cByobn+4LkVoAEZk3DU2=kwbcdb4m1b2c...@mail.gmail.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH v2] build: Haiku build fix
Type: series
Message-id: CA+XhMqy_bAnWm3cByobn+
>From f249bb9dc67a5d96b55e8b7faef3887c39a6de2c Mon Sep 17 00:00:00 2001
From: David Carlier
Date: Thu, 25 Jun 2020 19:32:42 +
Subject: [PATCH] build: haiku system build fix
Most of missing features resides in the bsd library.
Also defining constant equivalence.
Signed-off-by: David Carlier
> On Jun 25, 2020, at 1:37 PM, Richard Henderson
> wrote:
>
> On 6/25/20 10:00 AM, Lijun Pan wrote:
>> +#define VDIV_MOD_DO(name, op, element, sign, bit) \
>> +void helper_v##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
>> +{
> On Jun 25, 2020, at 1:25 PM, Richard Henderson
> wrote:
>
> On 6/25/20 10:00 AM, Lijun Pan wrote:
>> vmulld: Vector Multiply Low Doubleword.
>>
>> Signed-off-by: Lijun Pan
>> ---
>> v3: use tcg_gen_gvec_mul()
>>
>> target/ppc/translate/vmx-impl.inc.c | 1 +
>> target/ppc/translate/vmx-ops.
> On Jun 25, 2020, at 12:40 PM, Richard Henderson
> wrote:
>
> On 6/25/20 10:00 AM, Lijun Pan wrote:
>> +/* POWER ISA 3.1
>> */
>> +PPC2_ISA310= 0x0010ULL,
>
> This goes in the first patch, but...
>
>> #def
> On Jun 25, 2020, at 12:42 PM, Richard Henderson
> wrote:
>
> On 6/25/20 10:00 AM, Lijun Pan wrote:
>> +static void gen_brh(DisasContext *ctx)
>> +{
>> +TCGv_i64 t0 = tcg_temp_new_i64();
>> +TCGv_i64 t1 = tcg_temp_new_i64();
>> +TCGv_i64 t2 = tcg_temp_new_i64();
>> +
>> +tcg_
On Thu, 25 Jun 2020 at 00:06, Michael S. Tsirkin wrote:
>
> The following changes since commit d4b78317b7cf8c0c635b70086503813f79ff21ec:
>
> Merge remote-tracking branch
> 'remotes/pmaydell/tags/pull-target-arm-20200623' into staging (2020-06-23
> 18:57:05 +0100)
>
> are available in the Git r
On Thu, 25 Jun 2020 at 19:37, David CARLIER wrote:
>
> From 25adbdcdc17ef51a41759f16576901338ed8a469 Mon Sep 17 00:00:00 2001
> From: David Carlier
> Date: Thu, 25 Jun 2020 19:32:42 +
> Subject: [PATCH] build: haiku system build fix
>
> Most of missing features resides in the bsd library.
> A
On Thu, Jun 25, 2020 at 12:50 PM Alistair Francis wrote:
>
> On Thu, Jun 25, 2020 at 11:38 AM Atish Patra wrote:
> >
> > Currently, all riscv machines except sifive_u have identical reset vector
> > code implementations with memory addresses being different for all machines.
> > They can be easil
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