Patchew URL: https://patchew.org/QEMU/20200626033144.790098-1-richard.hender...@linaro.org/
Hi, This series seems to have some coding style problems. See output below for more information: Subject: [PATCH v9 00/46] target/arm: Implement ARMv8.5-MemTag, system mode Type: series Message-id: 20200626033144.790098-1-richard.hender...@linaro.org === TEST SCRIPT BEGIN === #!/bin/bash git rev-parse base > /dev/null || exit 0 git config --local diff.renamelimit 0 git config --local diff.renames True git config --local diff.algorithm histogram ./scripts/checkpatch.pl --mailback base.. === TEST SCRIPT END === Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384 From https://github.com/patchew-project/qemu * [new tag] patchew/20200626033144.790098-1-richard.hender...@linaro.org -> patchew/20200626033144.790098-1-richard.hender...@linaro.org Switched to a new branch 'test' 19fd148 target/arm: Add arm,armv8.5-memtag to dtb 68e0e2c target/arm: Enable MTE fd1e477 target/arm: Add allocation tag storage for system mode b4a8eba target/arm: Create tagged ram when MTE is enabled 2ccff60 target/arm: Cache the Tagged bit for a page in MemTxAttrs 3154906 target/arm: Always pass cacheattr to get_phys_addr 9767e94 target/arm: Set PSTATE.TCO on exception entry 38e0afb target/arm: Implement data cache set allocation tags 6539e61 target/arm: Complete TBI clearing for user-only for SVE 9cb3267 target/arm: Add mte helpers for sve scatter/gather memory ops 68c5348 target/arm: Handle TBI for sve scalar + int memory ops cdbe6a4 target/arm: Add mte helpers for sve scalar + int ff/nf loads a38fad7 target/arm: Add mte helpers for sve scalar + int stores 0afc0c0 target/arm: Add mte helpers for sve scalar + int loads a54faf2 target/arm: Add arm_tlb_bti_gp ddc3017 target/arm: Tidy trans_LD1R_zpri 6fe827e target/arm: Use mte_check1 for sve LD1R 20dcf79 target/arm: Use mte_checkN for sve unpredicated stores 05d0e79 target/arm: Use mte_checkN for sve unpredicated loads c0ebb0f target/arm: Add helper_mte_check_zva 664685f target/arm: Implement helper_mte_checkN a7d6539 target/arm: Implement helper_mte_check1 f8b9d7f target/arm: Add gen_mte_checkN 9c2dcf8 target/arm: Add gen_mte_check1 447016c target/arm: Move regime_tcr to internals.h 12956a4 target/arm: Move regime_el to internals.h c886a2f target/arm: Implement the access tag cache flushes 89f063e target/arm: Implement the LDGM, STGM, STZGM instructions b2d4fba target/arm: Simplify DC_ZVA 73c7897 target/arm: Restrict the values of DCZID.BS under TCG 79e377e target/arm: Implement the STGP instruction 665a07a target/arm: Implement LDG, STG, ST2G instructions 144ee8d target/arm: Define arm_cpu_do_unaligned_access for user-only 6396699 target/arm: Implement the SUBP instruction 0ee3f9e target/arm: Implement the GMI instruction 6b20749 target/arm: Implement the ADDG, SUBG instructions c83fbd1 target/arm: Revise decoding for disas_add_sub_imm 1a0adea target/arm: Implement the IRG instruction dceed31 target/arm: Add MTE bits to tb_flags e55acda target/arm: Add MTE system registers d6e7faa target/arm: Add DISAS_UPDATE_NOCHAIN 5a5c51e target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT 32aa9ac target/arm: Add support for MTE to HCR_EL2 and SCR_EL3 06cb0fb target/arm: Add support for MTE to SCTLR_ELx b7cbaa3 target/arm: Improve masking of SCR RES0 bits a5a2984 target/arm: Add isar tests for mte === OUTPUT BEGIN === 1/46 Checking commit a5a2984f9455 (target/arm: Add isar tests for mte) 2/46 Checking commit b7cbaa3a682e (target/arm: Improve masking of SCR RES0 bits) 3/46 Checking commit 06cb0fb346a8 (target/arm: Add support for MTE to SCTLR_ELx) 4/46 Checking commit 32aa9acf6271 (target/arm: Add support for MTE to HCR_EL2 and SCR_EL3) 5/46 Checking commit 5a5c51e63099 (target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT) 6/46 Checking commit d6e7faab1b43 (target/arm: Add DISAS_UPDATE_NOCHAIN) 7/46 Checking commit e55acdacb7c9 (target/arm: Add MTE system registers) 8/46 Checking commit dceed31be681 (target/arm: Add MTE bits to tb_flags) 9/46 Checking commit 1a0adea085f2 (target/arm: Implement the IRG instruction) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #45: new file mode 100644 total: 0 errors, 1 warnings, 120 lines checked Patch 9/46 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 10/46 Checking commit c83fbd1393b9 (target/arm: Revise decoding for disas_add_sub_imm) 11/46 Checking commit 6b207499c349 (target/arm: Implement the ADDG, SUBG instructions) 12/46 Checking commit 0ee3f9e74933 (target/arm: Implement the GMI instruction) 13/46 Checking commit 639669971961 (target/arm: Implement the SUBP instruction) 14/46 Checking commit 144ee8d3ccfa (target/arm: Define arm_cpu_do_unaligned_access for user-only) 15/46 Checking commit 665a07ad2896 (target/arm: Implement LDG, STG, ST2G instructions) 16/46 Checking commit 79e377e20409 (target/arm: Implement the STGP instruction) 17/46 Checking commit 73c7897861d4 (target/arm: Restrict the values of DCZID.BS under TCG) 18/46 Checking commit b2d4fba2a927 (target/arm: Simplify DC_ZVA) 19/46 Checking commit 89f063e1e72e (target/arm: Implement the LDGM, STGM, STZGM instructions) 20/46 Checking commit c886a2f2ae59 (target/arm: Implement the access tag cache flushes) 21/46 Checking commit 12956a4f828d (target/arm: Move regime_el to internals.h) 22/46 Checking commit 447016cebd06 (target/arm: Move regime_tcr to internals.h) 23/46 Checking commit 9c2dcf860acd (target/arm: Add gen_mte_check1) 24/46 Checking commit f8b9d7f9cea2 (target/arm: Add gen_mte_checkN) 25/46 Checking commit a7d65393dc26 (target/arm: Implement helper_mte_check1) 26/46 Checking commit 664685fb8d82 (target/arm: Implement helper_mte_checkN) 27/46 Checking commit c0ebb0fde795 (target/arm: Add helper_mte_check_zva) 28/46 Checking commit 05d0e794c710 (target/arm: Use mte_checkN for sve unpredicated loads) 29/46 Checking commit 20dcf793ab36 (target/arm: Use mte_checkN for sve unpredicated stores) 30/46 Checking commit 6fe827ec2022 (target/arm: Use mte_check1 for sve LD1R) 31/46 Checking commit ddc301735076 (target/arm: Tidy trans_LD1R_zpri) 32/46 Checking commit a54faf2d1d6b (target/arm: Add arm_tlb_bti_gp) 33/46 Checking commit 0afc0c0f79ec (target/arm: Add mte helpers for sve scalar + int loads) 34/46 Checking commit a38fad7262d9 (target/arm: Add mte helpers for sve scalar + int stores) 35/46 Checking commit cdbe6a4813d5 (target/arm: Add mte helpers for sve scalar + int ff/nf loads) 36/46 Checking commit 68c5348ab6db (target/arm: Handle TBI for sve scalar + int memory ops) 37/46 Checking commit 9cb3267a22fe (target/arm: Add mte helpers for sve scatter/gather memory ops) 38/46 Checking commit 6539e614c022 (target/arm: Complete TBI clearing for user-only for SVE) ERROR: spaces required around that '*' (ctx:VxV) #57: FILE: target/arm/sve_helper.c:3978: + (TYPEM)*(TYPEE *)(vd + H(reg_off)), ra); \ ^ total: 1 errors, 0 warnings, 57 lines checked Patch 38/46 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 39/46 Checking commit 38e0afbd1936 (target/arm: Implement data cache set allocation tags) 40/46 Checking commit 9767e94f1b3c (target/arm: Set PSTATE.TCO on exception entry) 41/46 Checking commit 3154906b1681 (target/arm: Always pass cacheattr to get_phys_addr) 42/46 Checking commit 2ccff60ed0a9 (target/arm: Cache the Tagged bit for a page in MemTxAttrs) 43/46 Checking commit b4a8ebafa261 (target/arm: Create tagged ram when MTE is enabled) 44/46 Checking commit fd1e477dc716 (target/arm: Add allocation tag storage for system mode) 45/46 Checking commit 68e0e2c8654f (target/arm: Enable MTE) 46/46 Checking commit 19fd1487595d (target/arm: Add arm,armv8.5-memtag to dtb) === OUTPUT END === Test command exited with code: 1 The full log is available at http://patchew.org/logs/20200626033144.790098-1-richard.hender...@linaro.org/testing.checkpatch/?type=message. --- Email generated automatically by Patchew [https://patchew.org/]. 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