> On Jun 25, 2020, at 12:40 PM, Richard Henderson
> <richard.hender...@linaro.org> wrote:
>
> On 6/25/20 10:00 AM, Lijun Pan wrote:
>> + /* POWER ISA 3.1
>> */
>> + PPC2_ISA310 = 0x0000000000100000ULL,
>
> This goes in the first patch, but...
>
>> #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX |
>> \
>> PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
>> @@ -2199,7 +2201,7 @@ enum {
>> PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
>> PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
>> PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
>> - PPC2_ISA300)
>> + PPC2_ISA300 | PPC2_ISA310)
>
> ... all of the rest belongs in a separate patch, which will be sorted to the
> end of the patch set.
>
Do you mean the first patch has
“
>> + /* POWER ISA 3.1
>> */
>> + PPC2_ISA310 = 0x0000000000100000ULL,
“
the second patch has
“
>> #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX |
>> \
>> PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
>> @@ -2199,7 +2201,7 @@ enum {
>> PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
>> PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
>> PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
>> - PPC2_ISA300)
>> + PPC2_ISA300 | PPC2_ISA310)
+++ b/target/ppc/translate_init.inc.c
@@ -9206,7 +9206,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
- PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL;
+ PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310;
"
> It's ok to keep the second patch at the beginning during development, so that
> you can test each instruction as you add it. But for final commit you do not
> want to enable the feature until it is complete.
>
Do you mean not submiting the second patch until all the instructions are
enabled in the future?
Lijun
