On 6/25/20 2:13 PM, Lijun Pan wrote:
>>> case INDEX_op_mul_vec:
>>> - tcg_debug_assert(vece == MO_32 && have_isa_2_07);
>>> - insn = VMULUWM;
>>> + tcg_debug_assert((vece == MO_32 && have_isa_2_07) ||
>>> + (vece == MO_64 && have_isa_3_10));
>>> + insn = mul_op[vece];
>>
>> I think it would be ok to just index mul_op here, since the real isa check is
>> to be done elsewhere.
>
> Just keep "insn = mul_op[vece];"
> and remove" tcg_debug_assert((vece == MO_32 && have_isa_2_07) ||
> (vece == MO_64 && have_isa_3_10));“?
Yes.
> @@ -3016,6 +3016,8 @@int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,
> unsigned vece)
> return -1;
> case MO_32:
> return have_isa_2_07 ? 1 : -1;
> + case MO_64:
> + return have_isa_3_10 ? 1 : -1;
> }
Actually, just "return have_isa_3_10".
Returning 1 means that the opcode is supported directly. Returning -1 means
that the opcode can be expanded by tcg_expand_vec_op. Returning 0 means that
the tcg backend does not support the opcode at all.
> something like below?
> @@ -3712,6 +3712,11 @@static void tcg_target_init(TCGContext *s)
> have_isa = tcg_isa_3_00;
> }
> #endif
> +#ifdef PPC_FEATURE2_ARCH_3_10
> + if (hwcap2 & PPC_FEATURE2_ARCH_3_10) {
> + have_isa = tcg_isa_3_10;
> + }
> +#endif
Certainly this.
> @@ -554,6 +554,7 @@typedef struct {
> #define PPC_FEATURE2_HTM_NOSC 0x01000000
> #define PPC_FEATURE2_ARCH_3_00 0x00800000
> #define PPC_FEATURE2_HAS_IEEE128 0x00400000
> +#define PPC_FEATURE2_ARCH_3_10 0x00200000
Of this I'm not sure. I didn't even realize these defines were here in
include/elf.h. For other tcg backends we get the defines from <sys/auxv.h>.
If we do want to update include/elf.h, it should be a separate patch. CC'ing
Laurent for this.
r~
