Version 9 incorporates some review:
* Adjust some commentary.
* Added an assert for tbi in aarch64_tr_init_disas_context
* Split arm,armv8.5-memtag to a new, final, patch. We might
just leave this one out of qemu mainline until the kernel
patch set that requires it gets merged.
r~
Richard Henderson (46):
target/arm: Add isar tests for mte
target/arm: Improve masking of SCR RES0 bits
target/arm: Add support for MTE to SCTLR_ELx
target/arm: Add support for MTE to HCR_EL2 and SCR_EL3
target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT
target/arm: Add DISAS_UPDATE_NOCHAIN
target/arm: Add MTE system registers
target/arm: Add MTE bits to tb_flags
target/arm: Implement the IRG instruction
target/arm: Revise decoding for disas_add_sub_imm
target/arm: Implement the ADDG, SUBG instructions
target/arm: Implement the GMI instruction
target/arm: Implement the SUBP instruction
target/arm: Define arm_cpu_do_unaligned_access for user-only
target/arm: Implement LDG, STG, ST2G instructions
target/arm: Implement the STGP instruction
target/arm: Restrict the values of DCZID.BS under TCG
target/arm: Simplify DC_ZVA
target/arm: Implement the LDGM, STGM, STZGM instructions
target/arm: Implement the access tag cache flushes
target/arm: Move regime_el to internals.h
target/arm: Move regime_tcr to internals.h
target/arm: Add gen_mte_check1
target/arm: Add gen_mte_checkN
target/arm: Implement helper_mte_check1
target/arm: Implement helper_mte_checkN
target/arm: Add helper_mte_check_zva
target/arm: Use mte_checkN for sve unpredicated loads
target/arm: Use mte_checkN for sve unpredicated stores
target/arm: Use mte_check1 for sve LD1R
target/arm: Tidy trans_LD1R_zpri
target/arm: Add arm_tlb_bti_gp
target/arm: Add mte helpers for sve scalar + int loads
target/arm: Add mte helpers for sve scalar + int stores
target/arm: Add mte helpers for sve scalar + int ff/nf loads
target/arm: Handle TBI for sve scalar + int memory ops
target/arm: Add mte helpers for sve scatter/gather memory ops
target/arm: Complete TBI clearing for user-only for SVE
target/arm: Implement data cache set allocation tags
target/arm: Set PSTATE.TCO on exception entry
target/arm: Always pass cacheattr to get_phys_addr
target/arm: Cache the Tagged bit for a page in MemTxAttrs
target/arm: Create tagged ram when MTE is enabled
target/arm: Add allocation tag storage for system mode
target/arm: Enable MTE
target/arm: Add arm,armv8.5-memtag to dtb
include/hw/arm/boot.h | 3 +
target/arm/cpu.h | 50 +-
target/arm/helper-a64.h | 16 +
target/arm/helper-sve.h | 488 ++++++++++++
target/arm/helper.h | 2 +
target/arm/internals.h | 153 +++-
target/arm/translate-a64.h | 5 +
target/arm/translate.h | 23 +-
hw/arm/boot.c | 12 +-
hw/arm/virt.c | 57 +-
target/arm/cpu.c | 81 +-
target/arm/cpu64.c | 5 +
target/arm/helper-a64.c | 94 +--
target/arm/helper.c | 423 +++++++---
target/arm/m_helper.c | 11 +-
target/arm/mte_helper.c | 906 +++++++++++++++++++++
target/arm/op_helper.c | 16 +
target/arm/sve_helper.c | 616 +++++++++++---
target/arm/tlb_helper.c | 13 +-
target/arm/translate-a64.c | 657 +++++++++++++--
target/arm/translate-sve.c | 1366 +++++++++++++++++++++-----------
target/arm/translate-vfp.inc.c | 4 +-
target/arm/translate.c | 16 +-
target/arm/Makefile.objs | 1 +
24 files changed, 4182 insertions(+), 836 deletions(-)
create mode 100644 target/arm/mte_helper.c
--
2.25.1
