attach the Elelemnt array buffer to vao.
This would fix most of(3 left) intel oglc vao test fail
[0]: http://www.opengl.org/registry/specs/ARB/vertex_array_object.txt
[1]: http://www.opengl.org/wiki/Vertex_Array_Object
Cc: i...@freedesktop.org
Signed-off-by: Yuanhan Liu
---
src/mesa/main/arrayobj
Signed-off-by: Yuanhan Liu
---
src/mesa/main/api_arrayelt.c |2 +-
src/mesa/main/api_validate.c | 14 ++--
src/mesa/main/arrayobj.c |4 +++
src/mesa/main/attrib.c|7 ++---
src/mesa/main/bufferobj.c |9 ++-
src/mesa/main/context.c |1 -
src
According opengl spec 4.2.pdf table 6.12 (Vertex Array Object State) at
page 515: the element buffer object is listed in vertex array object.
Add a testcase to test that.
Signed-off-by: Yuanhan Liu
---
tests/all.tests |1 +
tests/general/CMakeLists.gl.txt
On Tue, Nov 22, 2011 at 11:16:26AM -0700, Brian Paul wrote:
> On 11/22/2011 01:38 AM, Yuanhan Liu wrote:
> >This would make ElementArrayBufferObj data per vertex array object. I did't
> >find something to support this at the spec page[0]. But I did find
> >something th
On Wed, Nov 23, 2011 at 05:27:32PM +0800, Yuanhan Liu wrote:
> According opengl spec 4.2.pdf table 6.12 (Vertex Array Object State) at
> page 515: the element buffer object is listed in vertex array object.
>
> Add a testcase to test that.
>
> Signed-off-by: Yuanhan Liu
> -
On Wed, Nov 23, 2011 at 08:25:59AM -0700, Brian Paul wrote:
> On 11/23/2011 02:26 AM, Yuanhan Liu wrote:
> >According opengl spec 4.2.pdf table 6.12 (Vertex Array Object State) at
> >page 515, the element buffer object is listed in vertex array object.
> >
> >So, mov
On Wed, Nov 23, 2011 at 11:12:19AM -0800, Eric Anholt wrote:
> On Wed, 23 Nov 2011 17:34:30 +0800, Yuanhan Liu
> wrote:
> > From 9a1da8748f0faa23f34398213ff7ee45fda6bf36 Mon Sep 17 00:00:00 2001
> > From: Yuanhan Liu
> > Date: Wed, 23 Nov 2011 17:37:33 +0800
> >
On Wed, Nov 23, 2011 at 08:33:00AM -0700, Brian Paul wrote:
> On 11/23/2011 02:34 AM, Yuanhan Liu wrote:
> >+GLuint element;
> >+GLfloat vertics[] = {
>
> minor nit: s/vertics/vertices/
>
>
> >+-1, -1, 0,
> >+
On Wed, Nov 23, 2011 at 11:58:36AM -0800, Eric Anholt wrote:
> On Mon, 21 Nov 2011 16:27:57 +0800, Yuanhan Liu
> wrote:
> > Add a draw-pixel-with-texture testcase to check if texture
> > sampling is happened while drawing pixels by glDrawPixels.
> >
> > v2: use pig
> 3 files changed, 9 insertions(+), 9 deletions(-)
Reviewed-by: Yuanhan Liu
>
> diff --git a/src/mesa/main/bufferobj.c b/src/mesa/main/bufferobj.c
> index 4c77397..8e8fcd5 100644
> --- a/src/mesa/main/bufferobj.c
> +++ b/src/mesa/main/bufferobj.c
> @@ -1286,14 +1286,
On Thu, Nov 24, 2011 at 11:25:23AM -0800, Eric Anholt wrote:
> On Wed, 23 Nov 2011 12:24:37 -0700, Brian Paul wrote:
> > On 11/23/2011 12:12 PM, Eric Anholt wrote:
> > > On Wed, 23 Nov 2011 17:34:30 +0800, Yuanhan
> > > Liu wrote:
> > >> From 9a1da8748f0f
On Sat, Nov 26, 2011 at 09:01:51AM -0700, Brian Paul wrote:
> On 11/23/2011 06:15 PM, Yuanhan Liu wrote:
> >On Wed, Nov 23, 2011 at 08:25:59AM -0700, Brian Paul wrote:
> >>On 11/23/2011 02:26 AM, Yuanhan Liu wrote:
> >>>According opengl spec 4.2.pdf table 6.12
Silence the compile warning
Signed-off-by: Yuanhan Liu
---
src/glx/drisw_glx.c |1 -
1 files changed, 0 insertions(+), 1 deletions(-)
diff --git a/src/glx/drisw_glx.c b/src/glx/drisw_glx.c
index a150c61..7ba491b 100644
--- a/src/glx/drisw_glx.c
+++ b/src/glx/drisw_glx.c
@@ -304,7 +304,6
I didn't find anywhere use it anymore, remove it.
Signed-off-by: Yuanhan Liu
---
src/mesa/drivers/dri/i965/brw_eu.h |5 -
1 files changed, 0 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h
b/src/mesa/drivers/dri/i965/brw_eu.h
index dcb1fc9..8a446eb 1
Let if_stack just store the instruction pointer(an index). This is
somehow more flexible than store the instruction memory address.
This patch is mainly for the next patch.
Signed-off-by: Yuanhan Liu
---
src/mesa/drivers/dri/i965/brw_eu.c |3 +--
src/mesa/drivers/dri/i965/brw_eu.h
Increase the brw eu instruction store size dynamically instead of just
allocating it statically with a constant limit. This would fix something
that 'GL_MAX_PROGRAM_INSTRUCTIONS_ARB was 16384 while the driver would
limit it to 1'.
Signed-off-by: Yuanhan Liu
---
src/mesa/driver
On Tue, Nov 29, 2011 at 10:35:42AM -0800, Eric Anholt wrote:
> On Tue, 29 Nov 2011 16:08:38 +0800, Yuanhan Liu
> wrote:
> > Let if_stack just store the instruction pointer(an index). This is
> > somehow more flexible than store the instruction memory address.
>
> I'
On Tue, Nov 29, 2011 at 10:40:46AM -0800, Eric Anholt wrote:
> On Tue, 29 Nov 2011 16:08:39 +0800, Yuanhan Liu
> wrote:
> > Increase the brw eu instruction store size dynamically instead of just
> > allocating it statically with a constant limit. This would fix
Actually the first 5 patches are all prepare work for patch 6.
I checked those patches will all intel oglc testcases, and found no regressions.
What's better, it fixed something.
Yuanhan Liu (6):
i965: let all the brw_OPCODE functions return an instruction index
instead
i965: r
Let all the brw_OPCODE functions return an instruction index instead,
and use brw_insn_of(p, index) macro to reference the instruction stored
at p->store[].
This is a prepare work of let us increase the instruction store size
dynamically by reralloc.
Signed-off-by: Yuanhan Liu
---
src/m
Signed-off-by: Yuanhan Liu
---
src/mesa/drivers/dri/i965/brw_eu.h |2 +-
src/mesa/drivers/dri/i965/brw_eu_emit.c |2 +-
src/mesa/drivers/dri/i965/brw_fs_emit.cpp |2 +-
src/mesa/drivers/dri/i965/brw_vec4_emit.cpp |2 +-
src/mesa/drivers/dri/i965/brw_vs_emit.c
Let all the while loop stack just store the instruction index. This is
somehow more flexible than store the instruction memory address.
This is a prepare work of let us increase the instruction store size
dynamically by reralloc.
Signed-off-by: Yuanhan Liu
---
src/mesa/drivers/dri/i965
Let if_stack just store the instruction pointer(an index). This is
somehow more flexible than store the instruction memory address.
This is a prepare work of let us increase the instruction store size
dynamically by reralloc.
Signed-off-by: Yuanhan Liu
---
src/mesa/drivers/dri/i965/brw_eu.c
This is a prepare work of let us increase the instruction store size
dynamically by reralloc.
Signed-off-by: Yuanhan Liu
---
src/mesa/drivers/dri/i965/brw_eu.h |3 +--
src/mesa/drivers/dri/i965/brw_eu_emit.c |4 ++--
src/mesa/drivers/dri/i965/brw_sf_emit.c |8
src/mesa
Here is the final patch to increase the brw eu instruction store size
dynamically instead of just allocating it statically with a constant
limit. This would fix something like 'GL_MAX_PROGRAM_INSTRUCTIONS_ARB
was 16384 while the driver would limit it to 1'.
Signed-off-by: Y
andle some special
cases here, like brw_DO/JMPI, to let them return the instruction
index.
--
Yuanhan Liu (5):
i965: Add a help function brw_insn_index to get the instruction index
i965: prepare work for dynamic instruction store size on
IF/ELSE/ENDIF
i965: prepare work for dynamic instr
The reason to add a help function instead of just use 'insn - p->store'
instead is that this help function includes an assert.
Signed-off-by: Yuanhan Liu
---
src/mesa/drivers/dri/i965/brw_eu.h |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/src/mes
the instruction memory address.
Signed-off-by: Yuanhan Liu
---
src/mesa/drivers/dri/i965/brw_eu.c |3 +--
src/mesa/drivers/dri/i965/brw_eu.h |4 +++-
src/mesa/drivers/dri/i965/brw_eu_emit.c | 16
3 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/src/m
the loop_stack to
store the instruction index instead.
Signed-off-by: Yuanhan Liu
---
src/mesa/drivers/dri/i965/brw_clip_line.c |2 +-
src/mesa/drivers/dri/i965/brw_clip_tri.c |6 ++--
src/mesa/drivers/dri/i965/brw_clip_unfilled.c |4 +-
src/mesa/drivers/dri/i965/brw_e
-by: Yuanhan Liu
---
src/mesa/drivers/dri/i965/brw_eu.h |8 +---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 17 -
src/mesa/drivers/dri/i965/brw_sf_emit.c |2 +-
src/mesa/drivers/dri/i965/brw_wm_emit.c |2 +-
4 files changed, 15 insertions(+), 14 deletions(-)
d
it to 1'.
Signed-off-by: Yuanhan Liu
---
src/mesa/drivers/dri/i965/brw_eu.c |7 +++
src/mesa/drivers/dri/i965/brw_eu.h |7 ---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 22 +++---
3 files changed, 30 insertions(+), 6 deletions(-)
diff --git
On Fri, Dec 02, 2011 at 11:25:55AM -0800, Eric Anholt wrote:
> On Thu, 1 Dec 2011 18:26:50 +0800, Yuanhan Liu
> wrote:
> >
> > Actually the first 5 patches are all prepare work for patch 6.
> >
> > I checked those patches will all intel oglc testcases,
oglc test cases, and found
no regression. (Sandybridge only).
Thanks,
Yuanhan Liu
--
Eric Anholt (4):
i965: Drop unused do_insn argument from gen6_CONT().
i965: Don't make consumers of brw_DO()/brw_WHILE() track loop start
i965: Don't make consumers of brw_WHILE do pre-gen6
From: Eric Anholt
The branch distances get patched up later at the WHILE instruction.
Reviewed-by: Yuanhan Liu
---
src/mesa/drivers/dri/i965/brw_eu_emit.c |3 +--
src/mesa/drivers/dri/i965/brw_fs_emit.cpp |2 +-
src/mesa/drivers/dri/i965/brw_vec4_emit.cpp |2 +-
src/mesa
From: Eric Anholt
This is a similar cleanup to what we did for brw_IF(), brw_ELSE(),
brw_ENDIF() handling.
Reviewed-by: Yuanhan Liu
---
src/mesa/drivers/dri/i965/brw_clip_line.c |5 +--
src/mesa/drivers/dri/i965/brw_clip_tri.c | 15 +---
src/mesa/drivers/dri/i965
From: Eric Anholt
The EU code itself can just do this work, since all the consumers were
duplicating it.
Reviewed-by: Yuanhan Liu
---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 36 +-
src/mesa/drivers/dri/i965/brw_fs_emit.cpp | 33 +++-
src
From: Eric Anholt
The codegen backends all had this same tracking, so just do it at the
EU level.
Reviewed-by: Yuanhan Liu
---
src/mesa/drivers/dri/i965/brw_eu.c |1 +
src/mesa/drivers/dri/i965/brw_eu.h | 10 --
src/mesa/drivers/dri/i965/brw_eu_emit.c
ory address.
Signed-off-by: Yuanhan Liu
---
src/mesa/drivers/dri/i965/brw_eu.c |3 +--
src/mesa/drivers/dri/i965/brw_eu.h |4 +++-
src/mesa/drivers/dri/i965/brw_eu_emit.c | 22 +++---
3 files changed, 19 insertions(+), 10 deletions(-)
diff --git a/src/m
-by: Yuanhan Liu
---
src/mesa/drivers/dri/i965/brw_eu.h |8 +---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 17 -
src/mesa/drivers/dri/i965/brw_sf_emit.c |2 +-
src/mesa/drivers/dri/i965/brw_wm_emit.c |2 +-
4 files changed, 15 insertions(+), 14 deletions(-)
d
A single next_insn may change the base address of instruction store
memory(p->store), so call it first before referencing the instruction
store pointer from an index.
This the final prepare work to enable the dynamic store size.
Signed-off-by: Yuanhan Liu
---
src/mesa/drivers/dri/i
it to 1'.
Signed-off-by: Yuanhan Liu
---
src/mesa/drivers/dri/i965/brw_eu.c |7 +++
src/mesa/drivers/dri/i965/brw_eu.h |7 ---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 12 +++-
3 files changed, 22 insertions(+), 4 deletions(-)
diff --git a/src/mesa/d
On Wed, Dec 21, 2011 at 05:57:35AM -0800, Eric Anholt wrote:
> On Wed, 21 Dec 2011 17:33:41 +0800, Yuanhan Liu
> wrote:
> > If dynamic instruction store size is enabled, while after the brw_JMPI()
> > and before the brw_land_fwd_jump() function, the eu instruction store
> &g
For the case that index data is stored in element array buffer object,
and user called glMultiDrawElements, count the min/max_index before
calling vbo->draw_prims. vbo_get_minmax_index() isn't friendly to this
case. So do it while building the prim info.
Signed-off-by: Yuanhan Liu
---
On Thu, Dec 22, 2011 at 02:37:58PM -0800, Kenneth Graunke wrote:
> On 12/21/2011 01:33 AM, Yuanhan Liu wrote:
> > Hi, this is a new series of patches for dynamic eu instruction store
> > size. The first 4 is from Eric. I just grabed it to make it rebase to
> > current repo
On Thu, Dec 22, 2011 at 02:33:03PM -0800, Kenneth Graunke wrote:
> On 12/21/2011 01:33 AM, Yuanhan Liu wrote:
> > Here is the final patch to enable dynamic eu instruction store size:
> > increase the brw eu instruction store size dynamically instead of just
> > allocating
On Thu, Dec 22, 2011 at 11:09:12AM -0800, Kenneth Graunke wrote:
> On 12/21/2011 01:33 AM, Yuanhan Liu wrote:
> [snip]
> > + int emit_endif = 1;
>
> Please use bool and true/false rather than int.
Yes, right. Will fix it.
>
> > /* In single program flow mode,
On Thu, Dec 22, 2011 at 07:51:46PM -0800, Kenneth Graunke wrote:
> On 12/22/2011 07:04 PM, Yuanhan Liu wrote:
> > On Thu, Dec 22, 2011 at 02:33:03PM -0800, Kenneth Graunke wrote:
> >> On 12/21/2011 01:33 AM, Yuanhan Liu wrote:
> [snip]
> >>> -#define BRW_E
introduce vbo_sizeof_ib_type() function to return the index data type
size. I see some place use switch(ib->type) to get the index data type,
which is sort of duplicate.
Signed-off-by: Yuanhan Liu
---
src/mesa/state_tracker/st_draw.c | 15 +
src/mesa/state_trac
ses.
Signed-off-by: Yuanhan Liu
---
src/mesa/drivers/dri/i965/brw_draw.c | 18 --
1 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
b/src/mesa/drivers/dri/i965/brw_draw.c
index 621195d..3d0cc7c 100644
--- a/src/mesa/drivers/dri/i
On Tue, Dec 27, 2011 at 11:15:42AM -0800, Eric Anholt wrote:
> On Sun, 25 Dec 2011 12:26:25 +0800, Liu Aleaxander
> wrote:
> > On Sun, Dec 25, 2011 at 8:03 AM, Eric Anholt wrote:
> > > On Thu, 22 Dec 2011 18:55:50 +0800, Yuanhan Liu
> > > wrote:
> > >&
On Wed, Dec 28, 2011 at 12:07:08PM -0800, Eric Anholt wrote:
> On Wed, 28 Dec 2011 13:54:43 +0800, Yuanhan Liu
> wrote:
> > The current code would just calculate min/max_index for the first prim
> > unconditionally, which is wrong if nr_prims > 1.
> >
> > Th
On Thu, Dec 29, 2011 at 09:10:03AM +0100, Michel Dänzer wrote:
> On Don, 2011-12-29 at 10:03 +0800, Yuanhan Liu wrote:
> > On Wed, Dec 28, 2011 at 12:07:08PM -0800, Eric Anholt wrote:
> > > On Wed, 28 Dec 2011 13:54:43 +0800, Yuanhan Liu
> > > wrote:
> >
sue.
As when nr_prims = 1, we can pass 1 to paramter nr_prims, thus I made
vbo_get_minmax_index() static.
Signed-off-by: Yuanhan Liu
---
src/mesa/drivers/dri/i965/brw_draw.c |2 +-
src/mesa/drivers/dri/nouveau/nouveau_vbo_t.c |3 +-
src/mesa/main/api_validate.c
|2 +-
> src/mesa/state_tracker/st_manager.c|2 +-
> 14 files changed, 22 insertions(+), 23 deletions(-)
Reviewed-by: Yuanhan Liu
>
> diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c
> b/src/mesa/drivers/dri/intel/intel_tex_image.c
> inde
while, we may do some combine to reduce some
map/unmap.
> actually map the ib, you lose anyway). Hopefully won't hit that
> performance hog often...
> A comment inline.
>
>
> Am 31.12.2011 07:32, schrieb Yuanhan Liu:
[snip]...
> > + for (i = 0; i < nr_prims; i
On Wed, Jan 04, 2012 at 11:20:07AM +0800, Yuanhan Liu wrote:
> On Tue, Jan 03, 2012 at 08:25:31PM +0100, Roland Scheidegger wrote:
> > Ah index scanning...
> > I don't like that this will map/unmap the ib once for each prim,
> Me either :)
>
> > though
> >
On Wed, Jan 04, 2012 at 02:55:44PM -0700, Brian Paul wrote:
> We were wastefully mapping the whole source/dest buffers before.
> ---
> src/mesa/main/bufferobj.c | 12 ++--
> 1 files changed, 6 insertions(+), 6 deletions(-)
Looks good to me.
Reviewed-by: Yuanhan Liu
>
On Wed, Jan 04, 2012 at 07:23:24PM +0100, Roland Scheidegger wrote:
> Am 04.01.2012 04:59, schrieb Yuanhan Liu:
> > On Wed, Jan 04, 2012 at 11:20:07AM +0800, Yuanhan Liu wrote:
> >> On Tue, Jan 03, 2012 at 08:25:31PM +0100, Roland Scheidegger wrote:
> >>> Ah index
On Tue, Jan 10, 2012 at 08:43:18PM -0700, Brian Paul wrote:
> On Tue, Jan 3, 2012 at 8:59 PM, Yuanhan Liu
> wrote:
> > On Wed, Jan 04, 2012 at 11:20:07AM +0800, Yuanhan Liu wrote:
> >> On Tue, Jan 03, 2012 at 08:25:31PM +0100, Roland Scheidegger wrote:
> >> > Ah
: Yuanhan Liu
---
src/mesa/drivers/dri/i965/brw_defines.h |1 +
src/mesa/drivers/dri/i965/gen6_sf_state.c | 19 +--
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index 4d90a99
On Wed, Jan 18, 2012 at 06:23:52PM +0800, Yuanhan Liu wrote:
> When rendering to FBO, rendering is inverted. At the same time, we would
> also make sure the point sprite origin is inverted. Or, we will get an
> inverted result correspoinding to rendering to the default winsys FBO.
>
On Wed, Jan 18, 2012 at 12:13:28PM -0800, Ian Romanick wrote:
> On 01/18/2012 02:21 AM, Yuanhan Liu wrote:
> >On Wed, Jan 18, 2012 at 06:23:52PM +0800, Yuanhan Liu wrote:
> >>When rendering to FBO, rendering is inverted. At the same time, we would
> >>also make sure
On Wed, Jan 18, 2012 at 11:53:20AM -0800, Ian Romanick wrote:
> On 01/18/2012 02:23 AM, Yuanhan Liu wrote:
> >When rendering to FBO, rendering is inverted. At the same time, we would
> >also make sure the point sprite origin is inverted. Or, we will get an
> >inverted res
candidate for stable release branches.
v2: add the simliar logic to ivb, too (comments from Ian)
simplify the logic operation (comments from Brian)
Signed-off-by: Yuanhan Liu
---
src/mesa/drivers/dri/i965/brw_defines.h |1 +
src/mesa/drivers/dri/i965/gen6_sf_state.c | 15
On Thu, Jan 19, 2012 at 09:51:32AM -0800, Eric Anholt wrote:
> On Thu, 19 Jan 2012 10:30:53 +0800, Yuanhan Liu
> wrote:
> > When rendering to FBO, rendering is inverted. At the same time, we would
> > also make sure the point sprite origin is inverted. Or, we will get an
&
On Thu, Jan 19, 2012 at 10:32:30AM -0700, Brian Paul wrote:
> On 01/19/2012 10:17 AM, Ian Romanick wrote:
> >On 01/18/2012 06:30 PM, Yuanhan Liu wrote:
> >>When rendering to FBO, rendering is inverted. At the same time, we
> >>would
> >>also make sure the poi
candidate for stable release branches.
v2: add the simliar logic to ivb, too (comments from Ian)
simplify the logic operation (comments from Brian)
v3: pick a better comment from Eric
use != for the logic instead of ^ (comments from Ian)
Signed-off-by: Yuanhan Liu
---
src/mesa/drivers/dri
Fix the constant interpolation enable bit mask for flat light mode.
FRAG_BIT_COL0 attribute bit might be 0, in which case we need to
shift one more bit right.
This would fix the oglc specularColor test fail on both Sandybridge and
Ivybridge.
Signed-off-by: Yuanhan Liu
Signed-off-by: Xiang
for(; attr <
FRAG_ATTRIB_MAX; attr++) loop suggested by Eric.
Signed-off-by: Yuanhan Liu
Signed-off-by: Xiang, Haihao
---
src/mesa/drivers/dri/i965/gen6_sf_state.c | 19 +--
src/mesa/drivers/dri/i965/gen7_sf_state.c | 19 +--
2 files changed, 26 inserti
On Mon, Sep 05, 2011 at 10:41:03AM -0700, Eric Anholt wrote:
> On Mon, 5 Sep 2011 15:59:32 +0800, Yuanhan Liu
> wrote:
> > Fix the constant interpolation enable bit mask for flat light mode.
> > FRAG_BIT_COL0 attribute bit might be 0, in which case we need to
> >
Fix the constant interpolation enable bit mask for flat light mode.
FRAG_BIT_COL0 attribute bit might be 0, in which case we need to
shift one more bit right.
This would fix the oglc specularColor test fail on both Sandybridge and
Ivybridge.
Signed-off-by: Yuanhan Liu
Signed-off-by: Xiang
Store hw_prim info in brw context for other references. This patch is
mainly for the next patch.
Signed-off-by: Yuanhan Liu
---
src/mesa/drivers/dri/i965/brw_context.h |1 +
src/mesa/drivers/dri/i965/brw_draw.c| 17 +++--
2 files changed, 8 insertions(+), 10 deletions
UINT format.
This patch did 1, 2, but didn't do 3, 4. As it simply seems wrong to me
just change the last vetex element's component setting and source
element format.
Thoughts?
BTW, this patch fix the oglc pntrast fail on SNB(haven't tested it on
IVB yet).
Signed-off-by: Yuanha
patch.
This would fix the oglc divzero(basic.texQOrWEqualsZero) and
divzero(basic.texTrivialPrim) test case fail.
Signed-off-by: Yuanhan Liu
---
src/mesa/drivers/dri/intel/intel_tex_layout.c | 12
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/src/mesa/driver
On Thu, Sep 08, 2011 at 08:39:46AM -0700, Eric Anholt wrote:
> On Thu, 8 Sep 2011 11:00:52 +0800, Yuanhan Liu
> wrote:
> > This patch is just for RFC, as I am not sure it's the right way to setup
> > the edge flag enable bit in Vertex Element struture. Setting up thi
On Thu, Sep 08, 2011 at 01:16:23PM -0700, Ian Romanick wrote:
> -BEGIN PGP SIGNED MESSAGE-
> Hash: SHA1
>
> On 09/08/2011 03:16 AM, Yuanhan Liu wrote:
> > If user call glTexImage1D with width = 0 and height = 0(the last
> > level) like this: glTexImage1D(GL_TEXTUR
There is already comments show how to detect a null texture. Fix the
code to match the comments.
This would fix the oglc divzero(basic.texQOrWEqualsZero) and
divzero(basic.texTrivialPrim) test case fail.
Signed-off-by: Yuanhan Liu
---
src/mesa/drivers/dri/intel/intel_mipmap_tree.c |2 +-
1
On Fri, Sep 09, 2011 at 10:56:36AM +0800, Yuanhan Liu wrote:
> There is already comments show how to detect a null texture. Fix the
> code to match the comments.
>
> This would fix the oglc divzero(basic.texQOrWEqualsZero) and
> divzero(basic.texTrivialPrim) test case fail.
>
On Thu, Sep 08, 2011 at 09:12:44PM -0700, Kenneth Graunke wrote:
> On 09/08/2011 07:56 PM, Yuanhan Liu wrote:
> > There is already comments show how to detect a null texture. Fix the
> > code to match the comments.
> >
> > This would fix the oglc divzero(basic.texQOrW
On Thu, Sep 08, 2011 at 09:25:30PM -0700, Kenneth Graunke wrote:
> On 09/08/2011 06:59 PM, Yuanhan Liu wrote:
> > On Thu, Sep 08, 2011 at 08:39:46AM -0700, Eric Anholt wrote:
> >> On Thu, 8 Sep 2011 11:00:52 +0800, Yuanhan Liu
> >> wrote:
> >>> BTW, this
On Fri, Sep 09, 2011 at 10:08:38AM -0700, Eric Anholt wrote:
> On Fri, 9 Sep 2011 13:21:57 +0800, Yuanhan Liu
> wrote:
> > On Thu, Sep 08, 2011 at 09:25:30PM -0700, Kenneth Graunke wrote:
> > > On 09/08/2011 06:59 PM, Yuanhan Liu wrote:
> > > > On Thu, Sep 0
off-by: Yuanhan Liu
---
src/mesa/drivers/dri/i965/brw_state_upload.c | 11 +++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c
b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 76ffa0d..e34f190 100644
--- a/src/mesa/drivers/dr
oc failed.
Signed-off-by: Yuanhan Liu
---
src/mesa/main/dlist.c |9 +
src/mesa/main/pack.c | 27 ++-
2 files changed, 19 insertions(+), 17 deletions(-)
diff --git a/src/mesa/main/dlist.c b/src/mesa/main/dlist.c
index 6e075b4..21840e6 100644
--- a/src/mesa/mai
intel_image->mt might be NULL, say with border width set. It then would
trigger a segfault at intel_map/unmap_texture_image function.
This would fix the oglc misctest(basic.textureBorderIgnore) fail.
Signed-off-by: Yuanhan Liu
---
src/mesa/drivers/dri/intel/intel_tex.c |5 +++--
1 fi
The following patchs fixed some error handling for some gl functions.
Yuanhan Liu (8):
mesa: fix error handling for glBegin
mesa: fix error handling for glEvalMesh1/2D
mesa: fix error handling for some glGet* functions
mesa: fix error handling for glTexEnv
mesa: fix error handling for
According to opengl spec, trigger GL_INVALID_ENUM error if mode is not
one of those valid primitive mode while calling glBegin.
Signed-off-by: Yuanhan Liu
---
src/mesa/vbo/vbo_exec_api.c | 24
1 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/src/mesa
According man page, trigger error when calling glEvalMesh1/2D inside
glBegin/glEnd.
Signed-off-by: Yuanhan Liu
---
src/mesa/main/api_noop.c |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/src/mesa/main/api_noop.c b/src/mesa/main/api_noop.c
index 7d3d332..c4ac95c
According to the man page, it should trigger a GL_INVALID_OPERATION
while calling some glGet* functions inside glBegin and glEnd.
This patch dose handle the following functions:
glGetBooleanv
glGetFloatv
glGetIntegerv
glGetInteger64v
glGetDoublev
Signed-off-by: Yuanhan Liu
---
src/mesa
Fix error handling while calling glTexEnv with invalid texture
environment parameters.
Signed-off-by: Yuanhan Liu
---
src/mesa/main/texenv.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/src/mesa/main/texenv.c b/src/mesa/main/texenv.c
index c0d0f37..1df3890 100644
According the man page, GL_INVALID_OPERATION should be generated if
glIsEnabled is executed betwwen the execution of glBegin and the
correspoding execution of glEnd.
Signed-off-by: Yuanhan Liu
---
src/mesa/main/enable.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a
Trigger GL_INVALID_ENUM error if the face paramter is not a valid value.
Trigger GL_INVALID_VALUE error if the GL_SHININESS value is out side
[0,128].
Signed-off-by: Yuanhan Liu
---
src/mesa/vbo/vbo_attrib_tmp.h | 10 +-
1 files changed, 9 insertions(+), 1 deletions(-)
diff --git a
According the man page, GL_INVALID_OPERATION should generated if
glPixelZoom is executed between the execution of glBegin and the
corresponding execution of glEnd.
Signed-off-by: Yuanhan Liu
---
src/mesa/main/pixel.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/src
According the man page, trigger a GL_INVALID_VALUE if size < 0.
Signed-off-by: Yuanhan Liu
---
src/mesa/main/feedback.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/src/mesa/main/feedback.c b/src/mesa/main/feedback.c
index 597ec1e..d73aa08 100644
--- a/src/m
If I understand correctly, the new GL3 buffer object queries parameters,
like BUFFER_MAP_ACCESS_FLAGS, depends on ARB_map_buffer_range
extension.
Signed-off-by: Yuanhan Liu
---
src/mesa/main/bufferobj.c | 12 ++--
1 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/mesa
Accroding the man page, GL_INVALID_VALUE would generated if access has any
bits set other than those valid defined bits.
Signed-off-by: Yuanhan Liu
---
src/mesa/main/bufferobj.c | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/src/mesa/main/bufferobj.c b/src
On Mon, Sep 19, 2011 at 09:17:42AM -0700, Ian Romanick wrote:
> -BEGIN PGP SIGNED MESSAGE-
> Hash: SHA1
>
> On 09/19/2011 07:20 AM, Brian Paul wrote:
> > On 09/19/2011 04:25 AM, Yuanhan Liu wrote:
> >> If I understand correctly, the new GL3 buffer object qu
On Mon, Sep 19, 2011 at 11:54:44AM -0700, Eric Anholt wrote:
> On Mon, 19 Sep 2011 18:25:55 +0800, Yuanhan Liu
> wrote:
> > Accroding the man page, GL_INVALID_VALUE would generated if access has any
> > bits set other than those valid defined bits.
> >
> > Signe
On Mon, Sep 19, 2011 at 08:08:18AM -0600, Brian Paul wrote:
> On 09/19/2011 01:03 AM, Yuanhan Liu wrote:
> >Trigger GL_INVALID_ENUM error if the face paramter is not a valid value.
> >
> >Trigger GL_INVALID_VALUE error if the GL_SHININESS value is out side
> >[0,128].
&g
On Mon, Sep 19, 2011 at 08:09:09AM -0600, Brian Paul wrote:
> On 09/19/2011 01:02 AM, Yuanhan Liu wrote:
> >According to opengl spec, trigger GL_INVALID_ENUM error if mode is not
> >one of those valid primitive mode while calling glBegin.
> >
> >Signed-off-by: Yuanhan L
Trigger GL_INVALID_ENUM error if the face paramter is not a valid value.
Trigger GL_INVALID_VALUE error if the GL_SHININESS value is out side
[0, ctx->Constant.MaxShiniess].
v2: fix the max shininess value.
Signed-off-by: Yuanhan Liu
---
src/mesa/vbo/vbo_attrib_tmp.h | 11 ++-
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