If dynamic instruction store size is enabled, while after the brw_DO()
and before the brw_WHILE() function, the eu instruction store base
address(p->store) may change.
Thus let brw_DO return the instruction index and brw_WHILE take the
do_insn index as the second parameter. And also let the loop_stack to
store the instruction index instead.
Signed-off-by: Yuanhan Liu <yuanhan....@linux.intel.com>
---
src/mesa/drivers/dri/i965/brw_clip_line.c | 2 +-
src/mesa/drivers/dri/i965/brw_clip_tri.c | 6 ++--
src/mesa/drivers/dri/i965/brw_clip_unfilled.c | 4 +-
src/mesa/drivers/dri/i965/brw_eu.h | 9 ++-----
src/mesa/drivers/dri/i965/brw_eu_emit.c | 27 ++++++++++++++----------
src/mesa/drivers/dri/i965/brw_fs_emit.cpp | 11 ++++-----
src/mesa/drivers/dri/i965/brw_vec4_emit.cpp | 9 +++----
src/mesa/drivers/dri/i965/brw_vs_emit.c | 6 ++--
8 files changed, 37 insertions(+), 37 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_clip_line.c
b/src/mesa/drivers/dri/i965/brw_clip_line.c
index 75c64c0..c37ac53 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_line.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_line.c
@@ -132,7 +132,7 @@ static void clip_and_emit_line( struct brw_clip_compile *c )
struct brw_indirect newvtx0 = brw_indirect(2, 0);
struct brw_indirect newvtx1 = brw_indirect(3, 0);
struct brw_indirect plane_ptr = brw_indirect(4, 0);
- struct brw_instruction *plane_loop;
+ int plane_loop;
struct brw_reg v1_null_ud = retype(vec1(brw_null_reg()),
BRW_REGISTER_TYPE_UD);
GLuint hpos_offset = brw_vert_result_to_offset(&c->vue_map,
VERT_RESULT_HPOS);
diff --git a/src/mesa/drivers/dri/i965/brw_clip_tri.c
b/src/mesa/drivers/dri/i965/brw_clip_tri.c
index ffbfe94..3182a98 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_tri.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_tri.c
@@ -232,8 +232,8 @@ void brw_clip_tri( struct brw_clip_compile *c )
struct brw_indirect inlist_ptr = brw_indirect(4, 0);
struct brw_indirect outlist_ptr = brw_indirect(5, 0);
struct brw_indirect freelist_ptr = brw_indirect(6, 0);
- struct brw_instruction *plane_loop;
- struct brw_instruction *vertex_loop;
+ int plane_loop;
+ int vertex_loop;
GLuint hpos_offset = brw_vert_result_to_offset(&c->vue_map,
VERT_RESULT_HPOS);
@@ -404,7 +404,7 @@ void brw_clip_tri( struct brw_clip_compile *c )
void brw_clip_tri_emit_polygon(struct brw_clip_compile *c)
{
struct brw_compile *p = &c->func;
- struct brw_instruction *loop;
+ int loop;
/* for (loopcount = nr_verts-2; loopcount > 0; loopcount--)
*/
diff --git a/src/mesa/drivers/dri/i965/brw_clip_unfilled.c
b/src/mesa/drivers/dri/i965/brw_clip_unfilled.c
index ae84e19..d057695 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_unfilled.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_unfilled.c
@@ -273,7 +273,7 @@ static void emit_lines(struct brw_clip_compile *c,
bool do_offset)
{
struct brw_compile *p = &c->func;
- struct brw_instruction *loop;
+ int loop;
struct brw_indirect v0 = brw_indirect(0, 0);
struct brw_indirect v1 = brw_indirect(1, 0);
struct brw_indirect v0ptr = brw_indirect(2, 0);
@@ -338,7 +338,7 @@ static void emit_points(struct brw_clip_compile *c,
bool do_offset )
{
struct brw_compile *p = &c->func;
- struct brw_instruction *loop;
+ int loop;
struct brw_indirect v0 = brw_indirect(0, 0);
struct brw_indirect v0ptr = brw_indirect(2, 0);
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h
b/src/mesa/drivers/dri/i965/brw_eu.h
index 607ab96..19b919f 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -1009,16 +1009,13 @@ void brw_ENDIF(struct brw_compile *p);
/* DO/WHILE loops:
*/
-struct brw_instruction *brw_DO(struct brw_compile *p,
- GLuint execute_size);
+int brw_DO(struct brw_compile *p, GLuint execute_size);
-struct brw_instruction *brw_WHILE(struct brw_compile *p,
- struct brw_instruction *patch_insn);
+struct brw_instruction *brw_WHILE(struct brw_compile *p, int patch_insn_idx);
struct brw_instruction *brw_BREAK(struct brw_compile *p, int pop_count);
struct brw_instruction *brw_CONT(struct brw_compile *p, int pop_count);
-struct brw_instruction *gen6_CONT(struct brw_compile *p,
- struct brw_instruction *do_insn);
+struct brw_instruction *gen6_CONT(struct brw_compile *p);
/* Forward jumps:
*/
void brw_land_fwd_jump(struct brw_compile *p,
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 067111c..2acfacf 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -1220,8 +1220,7 @@ struct brw_instruction *brw_BREAK(struct brw_compile *p,
int pop_count)
return insn;
}
-struct brw_instruction *gen6_CONT(struct brw_compile *p,
- struct brw_instruction *do_insn)
+struct brw_instruction *gen6_CONT(struct brw_compile *p)
{
struct brw_instruction *insn;
@@ -1268,12 +1267,12 @@ struct brw_instruction *brw_CONT(struct brw_compile *p,
int pop_count)
* For gen6, there's no more mask stack, so no need for DO. WHILE
* just points back to the first instruction of the loop.
*/
-struct brw_instruction *brw_DO(struct brw_compile *p, GLuint execute_size)
+int brw_DO(struct brw_compile *p, GLuint execute_size)
{
struct intel_context *intel = &p->brw->intel;
if (intel->gen >= 6 || p->single_program_flow) {
- return &p->store[p->nr_insn];
+ return p->nr_insn;
} else {
struct brw_instruction *insn = next_insn(p, BRW_OPCODE_DO);
@@ -1289,16 +1288,16 @@ struct brw_instruction *brw_DO(struct brw_compile *p,
GLuint execute_size)
/* insn->header.mask_control = BRW_MASK_ENABLE; */
/* insn->header.mask_control = BRW_MASK_DISABLE; */
- return insn;
+ return brw_insn_index(p, insn);
}
}
-struct brw_instruction *brw_WHILE(struct brw_compile *p,
- struct brw_instruction *do_insn)
+struct brw_instruction *brw_WHILE(struct brw_compile *p, int do_insn_idx)
{
struct intel_context *intel = &p->brw->intel;
+ int insn_idx;
struct brw_instruction *insn;
GLuint br = 1;
@@ -1307,18 +1306,20 @@ struct brw_instruction *brw_WHILE(struct brw_compile *p,
if (intel->gen >= 7) {
insn = next_insn(p, BRW_OPCODE_WHILE);
+ insn_idx = brw_insn_index(p, insn);
brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src1(p, insn, brw_imm_ud(0));
- insn->bits3.break_cont.jip = br * (do_insn - insn);
+ insn->bits3.break_cont.jip = br * (do_insn_idx - insn_idx);
insn->header.execution_size = BRW_EXECUTE_8;
} else if (intel->gen == 6) {
insn = next_insn(p, BRW_OPCODE_WHILE);
+ insn_idx = brw_insn_index(p, insn);
brw_set_dest(p, insn, brw_imm_w(0));
- insn->bits1.branch_gen6.jump_count = br * (do_insn - insn);
+ insn->bits1.branch_gen6.jump_count = br * (do_insn_idx - insn_idx);
brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src1(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
@@ -1326,13 +1327,17 @@ struct brw_instruction *brw_WHILE(struct brw_compile *p,
} else {
if (p->single_program_flow) {
insn = next_insn(p, BRW_OPCODE_ADD);
+ insn_idx = brw_insn_index(p, insn);
brw_set_dest(p, insn, brw_ip_reg());
brw_set_src0(p, insn, brw_ip_reg());
- brw_set_src1(p, insn, brw_imm_d((do_insn - insn) * 16));
+ brw_set_src1(p, insn, brw_imm_d((do_insn_idx - insn_idx) * 16));
insn->header.execution_size = BRW_EXECUTE_1;
} else {
+ struct brw_instruction *do_insn;
insn = next_insn(p, BRW_OPCODE_WHILE);
+ insn_idx = brw_insn_index(p, insn);
+ do_insn = &p->store[do_insn_idx];
assert(do_insn->header.opcode == BRW_OPCODE_DO);
@@ -1341,7 +1346,7 @@ struct brw_instruction *brw_WHILE(struct brw_compile *p,
brw_set_src1(p, insn, brw_imm_d(0));
insn->header.execution_size = do_insn->header.execution_size;
- insn->bits3.if_else.jump_count = br * (do_insn - insn + 1);
+ insn->bits3.if_else.jump_count = br * (do_insn_idx - insn_idx + 1);
insn->bits3.if_else.pop_count = 0;
insn->bits3.if_else.pad0 = 0;
}
diff --git a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
index 1ac215e..78fc227 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
@@ -641,8 +641,7 @@ fs_visitor::generate_code()
int loop_stack_array_size = 16;
int loop_stack_depth = 0;
- brw_instruction **loop_stack =
- rzalloc_array(this->mem_ctx, brw_instruction *, loop_stack_array_size);
+ int *loop_stack = rzalloc_array(this->mem_ctx, int, loop_stack_array_size);
int *if_depth_in_loop =
rzalloc_array(this->mem_ctx, int, loop_stack_array_size);
@@ -781,7 +780,7 @@ fs_visitor::generate_code()
loop_stack[loop_stack_depth++] = brw_DO(p, BRW_EXECUTE_8);
if (loop_stack_array_size <= loop_stack_depth) {
loop_stack_array_size *= 2;
- loop_stack = reralloc(this->mem_ctx, loop_stack, brw_instruction *,
+ loop_stack = reralloc(this->mem_ctx, loop_stack, int,
loop_stack_array_size);
if_depth_in_loop = reralloc(this->mem_ctx, if_depth_in_loop, int,
loop_stack_array_size);
@@ -796,7 +795,7 @@ fs_visitor::generate_code()
case BRW_OPCODE_CONTINUE:
/* FINISHME: We need to write the loop instruction support still. */
if (intel->gen >= 6)
- gen6_CONT(p, loop_stack[loop_stack_depth - 1]);
+ gen6_CONT(p);
else
brw_CONT(p, if_depth_in_loop[loop_stack_depth]);
brw_set_predicate_control(p, BRW_PREDICATE_NONE);
@@ -814,12 +813,12 @@ fs_visitor::generate_code()
inst0 = inst1 = brw_WHILE(p, loop_stack[loop_stack_depth]);
if (intel->gen < 6) {
/* patch all the BREAK/CONT instructions from last BGNLOOP */
- while (inst0 > loop_stack[loop_stack_depth]) {
+ while (brw_insn_index(p, inst0) > loop_stack[loop_stack_depth]) {
inst0--;
if (inst0->header.opcode == BRW_OPCODE_BREAK &&
inst0->bits3.if_else.jump_count == 0) {
inst0->bits3.if_else.jump_count = br * (inst1 - inst0 + 1);
- }
+ }
else if (inst0->header.opcode == BRW_OPCODE_CONTINUE &&
inst0->bits3.if_else.jump_count == 0) {
inst0->bits3.if_else.jump_count = br * (inst1 - inst0);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
index 54bbe13..c25a11c 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
@@ -678,8 +678,7 @@ vec4_visitor::generate_code()
int loop_stack_array_size = 16;
int loop_stack_depth = 0;
- brw_instruction **loop_stack =
- rzalloc_array(this->mem_ctx, brw_instruction *, loop_stack_array_size);
+ int *loop_stack = rzalloc_array(this->mem_ctx, int, loop_stack_array_size);
int *if_depth_in_loop =
rzalloc_array(this->mem_ctx, int, loop_stack_array_size);
@@ -812,7 +811,7 @@ vec4_visitor::generate_code()
loop_stack[loop_stack_depth++] = brw_DO(p, BRW_EXECUTE_8);
if (loop_stack_array_size <= loop_stack_depth) {
loop_stack_array_size *= 2;
- loop_stack = reralloc(this->mem_ctx, loop_stack, brw_instruction *,
+ loop_stack = reralloc(this->mem_ctx, loop_stack, int,
loop_stack_array_size);
if_depth_in_loop = reralloc(this->mem_ctx, if_depth_in_loop, int,
loop_stack_array_size);
@@ -827,7 +826,7 @@ vec4_visitor::generate_code()
case BRW_OPCODE_CONTINUE:
/* FINISHME: We need to write the loop instruction support still. */
if (intel->gen >= 6)
- gen6_CONT(p, loop_stack[loop_stack_depth - 1]);
+ gen6_CONT(p);
else
brw_CONT(p, if_depth_in_loop[loop_stack_depth]);
brw_set_predicate_control(p, BRW_PREDICATE_NONE);
@@ -845,7 +844,7 @@ vec4_visitor::generate_code()
inst0 = inst1 = brw_WHILE(p, loop_stack[loop_stack_depth]);
if (intel->gen < 6) {
/* patch all the BREAK/CONT instructions from last BGNLOOP */
- while (inst0 > loop_stack[loop_stack_depth]) {
+ while (brw_insn_index(p, inst0) > loop_stack[loop_stack_depth]) {
inst0--;
if (inst0->header.opcode == BRW_OPCODE_BREAK &&
inst0->bits3.if_else.jump_count == 0) {
diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c
b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index e39b3dd..f5c7fd7 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -1844,7 +1844,7 @@ void brw_old_vs_emit(struct brw_vs_compile *c )
struct intel_context *intel = &brw->intel;
const GLuint nr_insns = c->vp->program.Base.NumInstructions;
GLuint insn, loop_depth = 0;
- struct brw_instruction *loop_inst[MAX_LOOP_DEPTH] = { 0 };
+ int loop_inst[MAX_LOOP_DEPTH] = { 0 };
int if_depth_in_loop[MAX_LOOP_DEPTH];
const struct brw_indirect stack_index = brw_indirect(0, 0);
GLuint index;
@@ -2106,7 +2106,7 @@ void brw_old_vs_emit(struct brw_vs_compile *c )
case OPCODE_CONT:
brw_set_predicate_control(p, get_predicate(inst));
if (intel->gen >= 6) {
- gen6_CONT(p, loop_inst[loop_depth - 1]);
+ gen6_CONT(p);
} else {
brw_CONT(p, if_depth_in_loop[loop_depth]);
}
@@ -2127,7 +2127,7 @@ void brw_old_vs_emit(struct brw_vs_compile *c )
if (intel->gen < 6) {
/* patch all the BREAK/CONT instructions from last BEGINLOOP */
- while (inst0 > loop_inst[loop_depth]) {
+ while (brw_insn_index(p, inst0) > loop_inst[loop_depth]) {
inst0--;
if (inst0->header.opcode == BRW_OPCODE_BREAK &&
inst0->bits3.if_else.jump_count == 0) {
--
1.7.4.4
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