Let all the brw_OPCODE functions return an instruction index instead,
and use brw_insn_of(p, index) macro to reference the instruction stored
at p->store[].
This is a prepare work of let us increase the instruction store size
dynamically by reralloc.
Signed-off-by: Yuanhan Liu <yuanhan....@linux.intel.com>
---
src/mesa/drivers/dri/i965/brw_clip_line.c | 2 +-
src/mesa/drivers/dri/i965/brw_clip_tri.c | 6 +-
src/mesa/drivers/dri/i965/brw_clip_unfilled.c | 6 +-
src/mesa/drivers/dri/i965/brw_eu.h | 32 ++--
src/mesa/drivers/dri/i965/brw_eu_emit.c | 194 ++++++++++++-------------
src/mesa/drivers/dri/i965/brw_fs_emit.cpp | 4 +-
src/mesa/drivers/dri/i965/brw_sf_emit.c | 6 +-
src/mesa/drivers/dri/i965/brw_vec4_emit.cpp | 12 +-
src/mesa/drivers/dri/i965/brw_vs_emit.c | 7 +-
src/mesa/drivers/dri/i965/brw_wm.h | 14 +-
src/mesa/drivers/dri/i965/brw_wm_emit.c | 16 +-
11 files changed, 146 insertions(+), 153 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_clip_line.c
b/src/mesa/drivers/dri/i965/brw_clip_line.c
index 75c64c0..4313637 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_line.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_line.c
@@ -160,7 +160,7 @@ static void clip_and_emit_line( struct brw_clip_compile *c )
brw_set_predicate_control(p, BRW_PREDICATE_NONE);
- plane_loop = brw_DO(p, BRW_EXECUTE_1);
+ plane_loop = brw_insn_of(p, brw_DO(p, BRW_EXECUTE_1));
{
/* if (planemask & 1)
*/
diff --git a/src/mesa/drivers/dri/i965/brw_clip_tri.c
b/src/mesa/drivers/dri/i965/brw_clip_tri.c
index ffbfe94..97eae35 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_tri.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_tri.c
@@ -244,7 +244,7 @@ void brw_clip_tri( struct brw_clip_compile *c )
brw_MOV(p, get_addr_reg(freelist_ptr), brw_address(c->reg.vertex[3]) );
- plane_loop = brw_DO(p, BRW_EXECUTE_1);
+ plane_loop = brw_insn_of(p, brw_DO(p, BRW_EXECUTE_1));
{
/* if (planemask & 1)
*/
@@ -266,7 +266,7 @@ void brw_clip_tri( struct brw_clip_compile *c )
brw_MOV(p, c->reg.loopcount, c->reg.nr_verts);
brw_MOV(p, c->reg.nr_verts, brw_imm_ud(0));
- vertex_loop = brw_DO(p, BRW_EXECUTE_1);
+ vertex_loop = brw_insn_of(p, brw_DO(p, BRW_EXECUTE_1));
{
/* vtx = *input_ptr;
*/
@@ -427,7 +427,7 @@ void brw_clip_tri_emit_polygon(struct brw_clip_compile *c)
brw_ADD(p, get_addr_reg(vptr), get_addr_reg(vptr), brw_imm_uw(2));
brw_MOV(p, get_addr_reg(v0), deref_1uw(vptr, 0));
- loop = brw_DO(p, BRW_EXECUTE_1);
+ loop = brw_insn_of(p, brw_DO(p, BRW_EXECUTE_1));
{
brw_clip_emit_vue(c, v0, 1, 0, (_3DPRIM_TRIFAN << 2));
diff --git a/src/mesa/drivers/dri/i965/brw_clip_unfilled.c
b/src/mesa/drivers/dri/i965/brw_clip_unfilled.c
index ae84e19..2a984fe 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_unfilled.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_unfilled.c
@@ -285,7 +285,7 @@ static void emit_lines(struct brw_clip_compile *c,
brw_MOV(p, c->reg.loopcount, c->reg.nr_verts);
brw_MOV(p, get_addr_reg(v0ptr), brw_address(c->reg.inlist));
- loop = brw_DO(p, BRW_EXECUTE_1);
+ loop = brw_insn_of(p, brw_DO(p, BRW_EXECUTE_1));
{
brw_MOV(p, get_addr_reg(v0), deref_1uw(v0ptr, 0));
brw_ADD(p, get_addr_reg(v0ptr), get_addr_reg(v0ptr), brw_imm_uw(2));
@@ -307,7 +307,7 @@ static void emit_lines(struct brw_clip_compile *c,
brw_ADD(p, get_addr_reg(v1ptr), get_addr_reg(v1ptr),
retype(c->reg.nr_verts, BRW_REGISTER_TYPE_UW));
brw_MOV(p, deref_1uw(v1ptr, 0), deref_1uw(v0ptr, 0));
- loop = brw_DO(p, BRW_EXECUTE_1);
+ loop = brw_insn_of(p, brw_DO(p, BRW_EXECUTE_1));
{
brw_MOV(p, get_addr_reg(v0), deref_1uw(v0ptr, 0));
brw_MOV(p, get_addr_reg(v1), deref_1uw(v0ptr, 2));
@@ -346,7 +346,7 @@ static void emit_points(struct brw_clip_compile *c,
brw_MOV(p, c->reg.loopcount, c->reg.nr_verts);
brw_MOV(p, get_addr_reg(v0ptr), brw_address(c->reg.inlist));
- loop = brw_DO(p, BRW_EXECUTE_1);
+ loop = brw_insn_of(p, brw_DO(p, BRW_EXECUTE_1));
{
brw_MOV(p, get_addr_reg(v0), deref_1uw(v0ptr, 0));
brw_ADD(p, get_addr_reg(v0ptr), get_addr_reg(v0ptr), brw_imm_uw(2));
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h
b/src/mesa/drivers/dri/i965/brw_eu.h
index 8a446eb..61d3178 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -797,7 +797,7 @@ void brw_init_compile(struct brw_context *, struct
brw_compile *p,
void *mem_ctx);
const GLuint *brw_get_program( struct brw_compile *p, GLuint *sz );
-struct brw_instruction *brw_next_insn(struct brw_compile *p, GLuint opcode);
+int brw_next_insn(struct brw_compile *p, GLuint opcode);
void brw_set_dest(struct brw_compile *p, struct brw_instruction *insn,
struct brw_reg dest);
void brw_set_src0(struct brw_compile *p, struct brw_instruction *insn,
@@ -807,15 +807,21 @@ void gen6_resolve_implied_move(struct brw_compile *p,
struct brw_reg *src,
GLuint msg_reg_nr);
+static inline struct brw_instruction *
+brw_insn_of(struct brw_compile *p, int index)
+{
+ return &p->store[index];
+}
+
/* Helpers for regular instructions:
*/
#define ALU1(OP) \
-struct brw_instruction *brw_##OP(struct brw_compile *p, \
+int brw_##OP(struct brw_compile *p, \
struct brw_reg dest, \
struct brw_reg src0);
#define ALU2(OP) \
-struct brw_instruction *brw_##OP(struct brw_compile *p, \
+int brw_##OP(struct brw_compile *p, \
struct brw_reg dest, \
struct brw_reg src0, \
struct brw_reg src1);
@@ -985,26 +991,22 @@ void brw_dp_READ_4_vs_relative(struct brw_compile *p,
/* If/else/endif. Works by manipulating the execution flags on each
* channel.
*/
-struct brw_instruction *brw_IF(struct brw_compile *p,
- GLuint execute_size);
-struct brw_instruction *gen6_IF(struct brw_compile *p, uint32_t conditional,
- struct brw_reg src0, struct brw_reg src1);
+int brw_IF(struct brw_compile *p, GLuint execute_size);
+int gen6_IF(struct brw_compile *p, uint32_t conditional,
+ struct brw_reg src0, struct brw_reg src1);
void brw_ELSE(struct brw_compile *p);
void brw_ENDIF(struct brw_compile *p);
/* DO/WHILE loops:
*/
-struct brw_instruction *brw_DO(struct brw_compile *p,
- GLuint execute_size);
+int brw_DO(struct brw_compile *p, GLuint execute_size);
-struct brw_instruction *brw_WHILE(struct brw_compile *p,
- struct brw_instruction *patch_insn);
+int brw_WHILE(struct brw_compile *p, struct brw_instruction *patch_insn);
-struct brw_instruction *brw_BREAK(struct brw_compile *p, int pop_count);
-struct brw_instruction *brw_CONT(struct brw_compile *p, int pop_count);
-struct brw_instruction *gen6_CONT(struct brw_compile *p,
- struct brw_instruction *do_insn);
+int brw_BREAK(struct brw_compile *p, int pop_count);
+int brw_CONT(struct brw_compile *p, int pop_count);
+int gen6_CONT(struct brw_compile *p, struct brw_instruction *do_insn);
/* Forward jumps:
*/
void brw_land_fwd_jump(struct brw_compile *p,
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 60350ca..4c0de2c 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -681,17 +681,16 @@ static void brw_set_sampler_message(struct brw_compile *p,
}
}
-
#define next_insn brw_next_insn
-struct brw_instruction *
-brw_next_insn(struct brw_compile *p, GLuint opcode)
+int brw_next_insn(struct brw_compile *p, GLuint opcode)
{
- struct brw_instruction *insn;
+ int insn;
assert(p->nr_insn + 1 < BRW_EU_MAX_INSN);
- insn = &p->store[p->nr_insn++];
- memcpy(insn, p->current, sizeof(*insn));
+ insn = p->nr_insn++;
+
+ memcpy(brw_insn_of(p, insn), p->current, sizeof(struct brw_instruction));
/* Reset this one-shot flag:
*/
@@ -701,32 +700,34 @@ brw_next_insn(struct brw_compile *p, GLuint opcode)
p->current->header.predicate_control = BRW_PREDICATE_NORMAL;
}
- insn->header.opcode = opcode;
+ brw_insn_of(p, insn)->header.opcode = opcode;
return insn;
}
-static struct brw_instruction *brw_alu1( struct brw_compile *p,
- GLuint opcode,
- struct brw_reg dest,
- struct brw_reg src )
+static int brw_alu1( struct brw_compile *p,
+ GLuint opcode,
+ struct brw_reg dest,
+ struct brw_reg src )
{
- struct brw_instruction *insn = next_insn(p, opcode);
+ int insn_idx = next_insn(p, opcode);
+ struct brw_instruction *insn = brw_insn_of(p, insn_idx);
brw_set_dest(p, insn, dest);
brw_set_src0(p, insn, src);
- return insn;
+ return insn_idx;
}
-static struct brw_instruction *brw_alu2(struct brw_compile *p,
- GLuint opcode,
- struct brw_reg dest,
- struct brw_reg src0,
- struct brw_reg src1 )
+static int brw_alu2(struct brw_compile *p,
+ GLuint opcode,
+ struct brw_reg dest,
+ struct brw_reg src0,
+ struct brw_reg src1 )
{
- struct brw_instruction *insn = next_insn(p, opcode);
+ int insn_idx = next_insn(p, opcode);
+ struct brw_instruction *insn = brw_insn_of(p, insn_idx);
brw_set_dest(p, insn, dest);
brw_set_src0(p, insn, src0);
brw_set_src1(p, insn, src1);
- return insn;
+ return insn_idx;
}
@@ -734,7 +735,7 @@ static struct brw_instruction *brw_alu2(struct brw_compile
*p,
* Convenience routines.
*/
#define ALU1(OP) \
-struct brw_instruction *brw_##OP(struct brw_compile *p, \
+int brw_##OP(struct brw_compile *p, \
struct brw_reg dest, \
struct brw_reg src0) \
{ \
@@ -742,7 +743,7 @@ struct brw_instruction *brw_##OP(struct brw_compile *p,
\
}
#define ALU2(OP) \
-struct brw_instruction *brw_##OP(struct brw_compile *p, \
+int brw_##OP(struct brw_compile *p, \
struct brw_reg dest, \
struct brw_reg src0, \
struct brw_reg src1) \
@@ -763,14 +764,14 @@ void brw_##OP(struct brw_compile *p,
\
struct brw_reg src) \
{ \
struct brw_instruction *rnd, *add; \
- rnd = next_insn(p, BRW_OPCODE_##OP);
\
+ rnd = brw_insn_of(p, next_insn(p, BRW_OPCODE_##OP));
\
brw_set_dest(p, rnd, dest); \
brw_set_src0(p, rnd, src); \
\
if (p->brw->intel.gen < 6) {
\
/* turn on round-increments */ \
rnd->header.destreg__conditionalmod = BRW_CONDITIONAL_R; \
- add = brw_ADD(p, dest, dest, brw_imm_f(1.0f)); \
+ add = brw_insn_of(p, brw_ADD(p, dest, dest, brw_imm_f(1.0f))); \
add->header.predicate_control = BRW_PREDICATE_NORMAL; \
} \
}
@@ -804,10 +805,10 @@ ROUND(RNDZ)
ROUND(RNDE)
-struct brw_instruction *brw_ADD(struct brw_compile *p,
- struct brw_reg dest,
- struct brw_reg src0,
- struct brw_reg src1)
+int brw_ADD(struct brw_compile *p,
+ struct brw_reg dest,
+ struct brw_reg src0,
+ struct brw_reg src1)
{
/* 6.2.2: add */
if (src0.type == BRW_REGISTER_TYPE_F ||
@@ -827,10 +828,10 @@ struct brw_instruction *brw_ADD(struct brw_compile *p,
return brw_alu2(p, BRW_OPCODE_ADD, dest, src0, src1);
}
-struct brw_instruction *brw_MUL(struct brw_compile *p,
- struct brw_reg dest,
- struct brw_reg src0,
- struct brw_reg src1)
+int brw_MUL(struct brw_compile *p,
+ struct brw_reg dest,
+ struct brw_reg src0,
+ struct brw_reg src1)
{
/* 6.32.38: mul */
if (src0.type == BRW_REGISTER_TYPE_D ||
@@ -865,7 +866,7 @@ struct brw_instruction *brw_MUL(struct brw_compile *p,
void brw_NOP(struct brw_compile *p)
{
- struct brw_instruction *insn = next_insn(p, BRW_OPCODE_NOP);
+ struct brw_instruction *insn = brw_insn_of(p, next_insn(p, BRW_OPCODE_NOP));
brw_set_dest(p, insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
brw_set_src0(p, insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
brw_set_src1(p, insn, brw_imm_ud(0x0));
@@ -879,12 +880,13 @@ void brw_NOP(struct brw_compile *p)
* Comparisons, if/else/endif
*/
-struct brw_instruction *brw_JMPI(struct brw_compile *p,
- struct brw_reg dest,
- struct brw_reg src0,
- struct brw_reg src1)
+int brw_JMPI(struct brw_compile *p,
+ struct brw_reg dest,
+ struct brw_reg src0,
+ struct brw_reg src1)
{
- struct brw_instruction *insn = brw_alu2(p, BRW_OPCODE_JMPI, dest, src0,
src1);
+ int insn_idx = brw_alu2(p, BRW_OPCODE_JMPI, dest, src0, src1);
+ struct brw_instruction *insn = brw_insn_of(p, insn_idx);
insn->header.execution_size = 1;
insn->header.compression_control = BRW_COMPRESSION_NONE;
@@ -892,7 +894,7 @@ struct brw_instruction *brw_JMPI(struct brw_compile *p,
p->current->header.predicate_control = BRW_PREDICATE_NONE;
- return insn;
+ return insn_idx;
}
static void
@@ -921,13 +923,11 @@ push_if_stack(struct brw_compile *p, struct
brw_instruction *inst)
* When the matching 'endif' instruction is reached, the flags are
* popped off. If the stack is now empty, normal execution resumes.
*/
-struct brw_instruction *
-brw_IF(struct brw_compile *p, GLuint execute_size)
+int brw_IF(struct brw_compile *p, GLuint execute_size)
{
struct intel_context *intel = &p->brw->intel;
- struct brw_instruction *insn;
-
- insn = next_insn(p, BRW_OPCODE_IF);
+ int insn_idx = next_insn(p, BRW_OPCODE_IF);
+ struct brw_instruction *insn = brw_insn_of(p, insn_idx);
/* Override the defaults for this instruction:
*/
@@ -958,19 +958,18 @@ brw_IF(struct brw_compile *p, GLuint execute_size)
p->current->header.predicate_control = BRW_PREDICATE_NONE;
push_if_stack(p, insn);
- return insn;
+ return insn_idx;
}
/* This function is only used for gen6-style IF instructions with an
* embedded comparison (conditional modifier). It is not used on gen7.
*/
-struct brw_instruction *
+int
gen6_IF(struct brw_compile *p, uint32_t conditional,
struct brw_reg src0, struct brw_reg src1)
{
- struct brw_instruction *insn;
-
- insn = next_insn(p, BRW_OPCODE_IF);
+ int insn_idx = next_insn(p, BRW_OPCODE_IF);;
+ struct brw_instruction *insn = brw_insn_of(p, insn_idx);
brw_set_dest(p, insn, brw_imm_w(0));
if (p->compressed) {
@@ -990,7 +989,7 @@ gen6_IF(struct brw_compile *p, uint32_t conditional,
insn->header.thread_control = BRW_THREAD_SWITCH;
push_if_stack(p, insn);
- return insn;
+ return insn_idx;
}
/**
@@ -1113,9 +1112,8 @@ void
brw_ELSE(struct brw_compile *p)
{
struct intel_context *intel = &p->brw->intel;
- struct brw_instruction *insn;
-
- insn = next_insn(p, BRW_OPCODE_ELSE);
+ int insn_idx = next_insn(p, BRW_OPCODE_ELSE);
+ struct brw_instruction *insn = brw_insn_of(p, insn_idx);
if (intel->gen < 6) {
brw_set_dest(p, insn, brw_ip_reg());
@@ -1164,7 +1162,7 @@ brw_ENDIF(struct brw_compile *p)
return;
}
- insn = next_insn(p, BRW_OPCODE_ENDIF);
+ insn = brw_insn_of(p, next_insn(p, BRW_OPCODE_ENDIF));
if (intel->gen < 6) {
brw_set_dest(p, insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
@@ -1197,12 +1195,12 @@ brw_ENDIF(struct brw_compile *p)
patch_IF_ELSE(p, if_inst, else_inst, insn);
}
-struct brw_instruction *brw_BREAK(struct brw_compile *p, int pop_count)
+int brw_BREAK(struct brw_compile *p, int pop_count)
{
struct intel_context *intel = &p->brw->intel;
- struct brw_instruction *insn;
+ int insn_idx = next_insn(p, BRW_OPCODE_BREAK);
+ struct brw_instruction *insn = brw_insn_of(p, insn_idx);
- insn = next_insn(p, BRW_OPCODE_BREAK);
if (intel->gen >= 6) {
brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
@@ -1217,15 +1215,14 @@ struct brw_instruction *brw_BREAK(struct brw_compile
*p, int pop_count)
insn->header.compression_control = BRW_COMPRESSION_NONE;
insn->header.execution_size = BRW_EXECUTE_8;
- return insn;
+ return insn_idx;
}
-struct brw_instruction *gen6_CONT(struct brw_compile *p,
- struct brw_instruction *do_insn)
+int gen6_CONT(struct brw_compile *p, struct brw_instruction *do_insn)
{
- struct brw_instruction *insn;
+ int insn_idx = next_insn(p, BRW_OPCODE_CONTINUE);
+ struct brw_instruction *insn = brw_insn_of(p, insn_idx);
- insn = next_insn(p, BRW_OPCODE_CONTINUE);
brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_dest(p, insn, brw_ip_reg());
@@ -1234,13 +1231,13 @@ struct brw_instruction *gen6_CONT(struct brw_compile *p,
insn->header.compression_control = BRW_COMPRESSION_NONE;
insn->header.execution_size = BRW_EXECUTE_8;
- return insn;
+ return insn_idx;
}
-struct brw_instruction *brw_CONT(struct brw_compile *p, int pop_count)
+int brw_CONT(struct brw_compile *p, int pop_count)
{
- struct brw_instruction *insn;
- insn = next_insn(p, BRW_OPCODE_CONTINUE);
+ int insn_idx = next_insn(p, BRW_OPCODE_CONTINUE);
+ struct brw_instruction *insn = brw_insn_of(p, insn_idx);
brw_set_dest(p, insn, brw_ip_reg());
brw_set_src0(p, insn, brw_ip_reg());
brw_set_src1(p, insn, brw_imm_d(0x0));
@@ -1249,7 +1246,7 @@ struct brw_instruction *brw_CONT(struct brw_compile *p,
int pop_count)
/* insn->header.mask_control = BRW_MASK_DISABLE; */
insn->bits3.if_else.pad0 = 0;
insn->bits3.if_else.pop_count = pop_count;
- return insn;
+ return insn_idx;
}
/* DO/WHILE loop:
@@ -1268,14 +1265,15 @@ struct brw_instruction *brw_CONT(struct brw_compile *p,
int pop_count)
* For gen6, there's no more mask stack, so no need for DO. WHILE
* just points back to the first instruction of the loop.
*/
-struct brw_instruction *brw_DO(struct brw_compile *p, GLuint execute_size)
+int brw_DO(struct brw_compile *p, GLuint execute_size)
{
struct intel_context *intel = &p->brw->intel;
if (intel->gen >= 6 || p->single_program_flow) {
- return &p->store[p->nr_insn];
+ return p->nr_insn;
} else {
- struct brw_instruction *insn = next_insn(p, BRW_OPCODE_DO);
+ int insn_idx = next_insn(p, BRW_OPCODE_DO);
+ struct brw_instruction *insn = brw_insn_of(p, insn_idx);
/* Override the defaults for this instruction:
*/
@@ -1289,25 +1287,23 @@ struct brw_instruction *brw_DO(struct brw_compile *p,
GLuint execute_size)
/* insn->header.mask_control = BRW_MASK_ENABLE; */
/* insn->header.mask_control = BRW_MASK_DISABLE; */
- return insn;
+ return insn_idx;
}
}
-struct brw_instruction *brw_WHILE(struct brw_compile *p,
- struct brw_instruction *do_insn)
+int brw_WHILE(struct brw_compile *p, struct brw_instruction *do_insn)
{
struct intel_context *intel = &p->brw->intel;
- struct brw_instruction *insn;
+ int insn_idx = next_insn(p, BRW_OPCODE_WHILE);
+ struct brw_instruction *insn = brw_insn_of(p, insn_idx);
GLuint br = 1;
if (intel->gen >= 5)
br = 2;
if (intel->gen >= 7) {
- insn = next_insn(p, BRW_OPCODE_WHILE);
-
brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src1(p, insn, brw_imm_ud(0));
@@ -1315,8 +1311,6 @@ struct brw_instruction *brw_WHILE(struct brw_compile *p,
insn->header.execution_size = BRW_EXECUTE_8;
} else if (intel->gen == 6) {
- insn = next_insn(p, BRW_OPCODE_WHILE);
-
brw_set_dest(p, insn, brw_imm_w(0));
insn->bits1.branch_gen6.jump_count = br * (do_insn - insn);
brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
@@ -1325,15 +1319,11 @@ struct brw_instruction *brw_WHILE(struct brw_compile *p,
insn->header.execution_size = BRW_EXECUTE_8;
} else {
if (p->single_program_flow) {
- insn = next_insn(p, BRW_OPCODE_ADD);
-
brw_set_dest(p, insn, brw_ip_reg());
brw_set_src0(p, insn, brw_ip_reg());
brw_set_src1(p, insn, brw_imm_d((do_insn - insn) * 16));
insn->header.execution_size = BRW_EXECUTE_1;
} else {
- insn = next_insn(p, BRW_OPCODE_WHILE);
-
assert(do_insn->header.opcode == BRW_OPCODE_DO);
brw_set_dest(p, insn, brw_ip_reg());
@@ -1349,7 +1339,7 @@ struct brw_instruction *brw_WHILE(struct brw_compile *p,
insn->header.compression_control = BRW_COMPRESSION_NONE;
p->current->header.predicate_control = BRW_PREDICATE_NONE;
- return insn;
+ return insn_idx;
}
@@ -1383,7 +1373,7 @@ void brw_CMP(struct brw_compile *p,
struct brw_reg src0,
struct brw_reg src1)
{
- struct brw_instruction *insn = next_insn(p, BRW_OPCODE_CMP);
+ struct brw_instruction *insn = brw_insn_of(p, next_insn(p, BRW_OPCODE_CMP));
insn->header.destreg__conditionalmod = conditional;
brw_set_dest(p, insn, dest);
@@ -1408,7 +1398,7 @@ void brw_CMP(struct brw_compile *p,
to wake up thread. */
void brw_WAIT (struct brw_compile *p)
{
- struct brw_instruction *insn = next_insn(p, BRW_OPCODE_WAIT);
+ struct brw_instruction *insn = brw_insn_of(p, next_insn(p,
BRW_OPCODE_WAIT));
struct brw_reg src = brw_notification_1_reg();
brw_set_dest(p, insn, src);
@@ -1438,7 +1428,7 @@ void brw_math( struct brw_compile *p,
struct intel_context *intel = &p->brw->intel;
if (intel->gen >= 6) {
- struct brw_instruction *insn = next_insn(p, BRW_OPCODE_MATH);
+ struct brw_instruction *insn = brw_insn_of(p, next_insn(p,
BRW_OPCODE_MATH));
assert(dest.file == BRW_GENERAL_REGISTER_FILE);
assert(src.file == BRW_GENERAL_REGISTER_FILE);
@@ -1471,7 +1461,7 @@ void brw_math( struct brw_compile *p,
brw_set_src0(p, insn, src);
brw_set_src1(p, insn, brw_null_reg());
} else {
- struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
+ struct brw_instruction *insn = brw_insn_of(p, next_insn(p,
BRW_OPCODE_SEND));
/* Example code doesn't set predicate_control for send
* instructions.
@@ -1500,7 +1490,7 @@ void brw_math2(struct brw_compile *p,
struct brw_reg src1)
{
struct intel_context *intel = &p->brw->intel;
- struct brw_instruction *insn = next_insn(p, BRW_OPCODE_MATH);
+ struct brw_instruction *insn = brw_insn_of(p, next_insn(p,
BRW_OPCODE_MATH));
assert(intel->gen >= 6);
(void) intel;
@@ -1560,7 +1550,7 @@ void brw_math_16( struct brw_compile *p,
struct brw_instruction *insn;
if (intel->gen >= 6) {
- insn = next_insn(p, BRW_OPCODE_MATH);
+ insn = brw_insn_of(p, next_insn(p, BRW_OPCODE_MATH));
/* Math is the same ISA format as other opcodes, except that CondModifier
* becomes FC[3:0] and ThreadCtrl becomes FC[5:4].
@@ -1584,7 +1574,7 @@ void brw_math_16( struct brw_compile *p,
brw_set_predicate_control_flag_value(p, 0xff);
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
- insn = next_insn(p, BRW_OPCODE_SEND);
+ insn = brw_insn_of(p, next_insn(p, BRW_OPCODE_SEND));
insn->header.destreg__conditionalmod = msg_reg_nr;
brw_set_dest(p, insn, dest);
@@ -1599,7 +1589,7 @@ void brw_math_16( struct brw_compile *p,
/* Second instruction:
*/
- insn = next_insn(p, BRW_OPCODE_SEND);
+ insn = brw_insn_of(p, next_insn(p, BRW_OPCODE_SEND));
insn->header.compression_control = BRW_COMPRESSION_2NDHALF;
insn->header.destreg__conditionalmod = msg_reg_nr+1;
@@ -1670,7 +1660,7 @@ void brw_oword_block_write_scratch(struct brw_compile *p,
{
struct brw_reg dest;
- struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
+ struct brw_instruction *insn = brw_insn_of(p, next_insn(p,
BRW_OPCODE_SEND));
int send_commit_msg;
struct brw_reg src_header = retype(brw_vec8_grf(0, 0),
BRW_REGISTER_TYPE_UW);
@@ -1777,7 +1767,7 @@ brw_oword_block_read_scratch(struct brw_compile *p,
}
{
- struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
+ struct brw_instruction *insn = brw_insn_of(p, next_insn(p,
BRW_OPCODE_SEND));
assert(insn->header.predicate_control == 0);
insn->header.compression_control = BRW_COMPRESSION_NONE;
@@ -1834,7 +1824,7 @@ void brw_oword_block_read(struct brw_compile *p,
2), BRW_REGISTER_TYPE_UD),
brw_imm_ud(offset));
- struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
+ struct brw_instruction *insn = brw_insn_of(p, next_insn(p,
BRW_OPCODE_SEND));
insn->header.destreg__conditionalmod = mrf.nr;
/* cast dest to a uword[8] vector */
@@ -1879,7 +1869,7 @@ void brw_dword_scattered_read(struct brw_compile *p,
brw_MOV(p, mrf, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
brw_pop_insn_state(p);
- struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
+ struct brw_instruction *insn = brw_insn_of(p, next_insn(p,
BRW_OPCODE_SEND));
insn->header.destreg__conditionalmod = mrf.nr;
/* cast dest to a uword[8] vector */
@@ -1928,7 +1918,7 @@ void brw_dp_READ_4_vs(struct brw_compile *p,
brw_imm_ud(location));
brw_pop_insn_state(p);
- insn = next_insn(p, BRW_OPCODE_SEND);
+ insn = brw_insn_of(p, next_insn(p, BRW_OPCODE_SEND));
insn->header.predicate_control = BRW_PREDICATE_NONE;
insn->header.compression_control = BRW_COMPRESSION_NONE;
@@ -1981,7 +1971,7 @@ void brw_dp_READ_4_vs_relative(struct brw_compile *p,
brw_pop_insn_state(p);
gen6_resolve_implied_move(p, &src, 0);
- struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
+ struct brw_instruction *insn = brw_insn_of(p, next_insn(p,
BRW_OPCODE_SEND));
insn->header.predicate_control = BRW_PREDICATE_NONE;
insn->header.compression_control = BRW_COMPRESSION_NONE;
@@ -2031,9 +2021,9 @@ void brw_fb_WRITE(struct brw_compile *p,
dest = retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW);
if (intel->gen >= 6 && binding_table_index == 0) {
- insn = next_insn(p, BRW_OPCODE_SENDC);
+ insn = brw_insn_of(p, next_insn(p, BRW_OPCODE_SENDC));
} else {
- insn = next_insn(p, BRW_OPCODE_SEND);
+ insn = brw_insn_of(p, next_insn(p, BRW_OPCODE_SEND));
}
/* The execution mask is ignored for render target writes. */
insn->header.predicate_control = 0;
@@ -2167,7 +2157,7 @@ void brw_SAMPLE(struct brw_compile *p,
gen6_resolve_implied_move(p, &src0, msg_reg_nr);
- insn = next_insn(p, BRW_OPCODE_SEND);
+ insn = brw_insn_of(p, next_insn(p, BRW_OPCODE_SEND));
insn->header.predicate_control = 0; /* XXX */
insn->header.compression_control = BRW_COMPRESSION_NONE;
if (intel->gen < 6)
@@ -2233,7 +2223,7 @@ void brw_urb_WRITE(struct brw_compile *p,
brw_pop_insn_state(p);
}
- insn = next_insn(p, BRW_OPCODE_SEND);
+ insn = brw_insn_of(p, next_insn(p, BRW_OPCODE_SEND));
assert(msg_length < BRW_MAX_MRF);
@@ -2347,7 +2337,7 @@ void brw_ff_sync(struct brw_compile *p,
gen6_resolve_implied_move(p, &src0, msg_reg_nr);
- insn = next_insn(p, BRW_OPCODE_SEND);
+ insn = brw_insn_of(p, next_insn(p, BRW_OPCODE_SEND));
brw_set_dest(p, insn, dest);
brw_set_src0(p, insn, src0);
brw_set_src1(p, insn, brw_imm_d(0));
diff --git a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
index 1ac215e..3b1577d 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
@@ -778,7 +778,7 @@ fs_visitor::generate_code()
break;
case BRW_OPCODE_DO:
- loop_stack[loop_stack_depth++] = brw_DO(p, BRW_EXECUTE_8);
+ loop_stack[loop_stack_depth++] = brw_insn_of(p, brw_DO(p,
BRW_EXECUTE_8));
if (loop_stack_array_size <= loop_stack_depth) {
loop_stack_array_size *= 2;
loop_stack = reralloc(this->mem_ctx, loop_stack, brw_instruction *,
@@ -811,7 +811,7 @@ fs_visitor::generate_code()
assert(loop_stack_depth > 0);
loop_stack_depth--;
- inst0 = inst1 = brw_WHILE(p, loop_stack[loop_stack_depth]);
+ inst0 = inst1 = brw_insn_of(p, brw_WHILE(p,
loop_stack[loop_stack_depth]));
if (intel->gen < 6) {
/* patch all the BREAK/CONT instructions from last BGNLOOP */
while (inst0 > loop_stack[loop_stack_depth]) {
diff --git a/src/mesa/drivers/dri/i965/brw_sf_emit.c
b/src/mesa/drivers/dri/i965/brw_sf_emit.c
index fe3341c..6570ad0 100644
--- a/src/mesa/drivers/dri/i965/brw_sf_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_sf_emit.c
@@ -738,7 +738,7 @@ void brw_emit_anyprim_setup( struct brw_sf_compile *c )
(1<<_3DPRIM_POLYGON) |
(1<<_3DPRIM_RECTLIST) |
(1<<_3DPRIM_TRIFAN_NOSTIPPLE)));
- jmp = brw_JMPI(p, ip, ip, brw_imm_d(0));
+ jmp = brw_insn_of(p, brw_JMPI(p, ip, ip, brw_imm_d(0)));
{
saveflag = p->flag_value;
brw_push_insn_state(p);
@@ -759,7 +759,7 @@ void brw_emit_anyprim_setup( struct brw_sf_compile *c )
(1<<_3DPRIM_LINESTRIP_CONT) |
(1<<_3DPRIM_LINESTRIP_BF) |
(1<<_3DPRIM_LINESTRIP_CONT_BF)));
- jmp = brw_JMPI(p, ip, ip, brw_imm_d(0));
+ jmp = brw_insn_of(p, brw_JMPI(p, ip, ip, brw_imm_d(0)));
{
saveflag = p->flag_value;
brw_push_insn_state(p);
@@ -772,7 +772,7 @@ void brw_emit_anyprim_setup( struct brw_sf_compile *c )
brw_set_conditionalmod(p, BRW_CONDITIONAL_Z);
brw_AND(p, v1_null_ud, payload_attr,
brw_imm_ud(1<<BRW_SPRITE_POINT_ENABLE));
- jmp = brw_JMPI(p, ip, ip, brw_imm_d(0));
+ jmp = brw_insn_of(p, brw_JMPI(p, ip, ip, brw_imm_d(0)));
{
saveflag = p->flag_value;
brw_push_insn_state(p);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
index 54bbe13..a279e87 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
@@ -433,7 +433,7 @@ vec4_visitor::generate_scratch_read(vec4_instruction *inst,
/* Each of the 8 channel enables is considered for whether each
* dword is written.
*/
- struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
+ struct brw_instruction *send = brw_insn_of(p, brw_next_insn(p,
BRW_OPCODE_SEND));
brw_set_dest(p, send, dst);
brw_set_src0(p, send, header);
if (intel->gen < 6)
@@ -503,7 +503,7 @@ vec4_visitor::generate_scratch_write(vec4_instruction *inst,
/* Each of the 8 channel enables is considered for whether each
* dword is written.
*/
- struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
+ struct brw_instruction *send = brw_insn_of(p, brw_next_insn(p,
BRW_OPCODE_SEND));
brw_set_dest(p, send, dst);
brw_set_src0(p, send, header);
if (intel->gen < 6)
@@ -544,7 +544,7 @@ vec4_visitor::generate_pull_constant_load(vec4_instruction
*inst,
/* Each of the 8 channel enables is considered for whether each
* dword is written.
*/
- struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
+ struct brw_instruction *send = brw_insn_of(p, brw_next_insn(p,
BRW_OPCODE_SEND));
brw_set_dest(p, send, dst);
brw_set_src0(p, send, header);
if (intel->gen < 6)
@@ -794,7 +794,7 @@ vec4_visitor::generate_code()
assert(intel->gen == 6);
gen6_IF(p, inst->conditional_mod, src[0], src[1]);
} else {
- struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8);
+ struct brw_instruction *brw_inst = brw_insn_of(p, brw_IF(p,
BRW_EXECUTE_8));
brw_inst->header.predicate_control = inst->predicate;
}
if_depth_in_loop[loop_stack_depth]++;
@@ -809,7 +809,7 @@ vec4_visitor::generate_code()
break;
case BRW_OPCODE_DO:
- loop_stack[loop_stack_depth++] = brw_DO(p, BRW_EXECUTE_8);
+ loop_stack[loop_stack_depth++] = brw_insn_of(p, brw_DO(p,
BRW_EXECUTE_8));
if (loop_stack_array_size <= loop_stack_depth) {
loop_stack_array_size *= 2;
loop_stack = reralloc(this->mem_ctx, loop_stack, brw_instruction *,
@@ -842,7 +842,7 @@ vec4_visitor::generate_code()
assert(loop_stack_depth > 0);
loop_stack_depth--;
- inst0 = inst1 = brw_WHILE(p, loop_stack[loop_stack_depth]);
+ inst0 = inst1 = brw_insn_of(p, brw_WHILE(p,
loop_stack[loop_stack_depth]));
if (intel->gen < 6) {
/* patch all the BREAK/CONT instructions from last BGNLOOP */
while (inst0 > loop_stack[loop_stack_depth]) {
diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c
b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index e39b3dd..0a0cfbe 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -2078,7 +2078,8 @@ void brw_old_vs_emit(struct brw_vs_compile *c )
emit_xpd(p, dst, args[0], args[1]);
break;
case OPCODE_IF: {
- struct brw_instruction *if_inst = brw_IF(p, BRW_EXECUTE_8);
+ struct brw_instruction *if_inst;
+ if_inst = brw_insn_of(p, brw_IF(p, BRW_EXECUTE_8));
/* Note that brw_IF smashes the predicate_control field. */
if_inst->header.predicate_control = get_predicate(inst);
if_depth_in_loop[loop_depth]++;
@@ -2095,7 +2096,7 @@ void brw_old_vs_emit(struct brw_vs_compile *c )
break;
case OPCODE_BGNLOOP:
clear_current_const(c);
- loop_inst[loop_depth++] = brw_DO(p, BRW_EXECUTE_8);
+ loop_inst[loop_depth++] = brw_insn_of(p, brw_DO(p, BRW_EXECUTE_8));
if_depth_in_loop[loop_depth] = 0;
break;
case OPCODE_BRK:
@@ -2123,7 +2124,7 @@ void brw_old_vs_emit(struct brw_vs_compile *c )
if (intel->gen == 5)
br = 2;
- inst0 = inst1 = brw_WHILE(p, loop_inst[loop_depth]);
+ inst0 = inst1 = brw_insn_of(p, brw_WHILE(p, loop_inst[loop_depth]));
if (intel->gen < 6) {
/* patch all the BREAK/CONT instructions from last BEGINLOOP */
diff --git a/src/mesa/drivers/dri/i965/brw_wm.h
b/src/mesa/drivers/dri/i965/brw_wm.h
index 5967592..34b3fa3 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.h
+++ b/src/mesa/drivers/dri/i965/brw_wm.h
@@ -330,17 +330,17 @@ bool brw_wm_fs_emit(struct brw_context *brw, struct
brw_wm_compile *c,
/* brw_wm_emit.c */
void emit_alu1(struct brw_compile *p,
- struct brw_instruction *(*func)(struct brw_compile *,
- struct brw_reg,
- struct brw_reg),
+ int (*func)(struct brw_compile *,
+ struct brw_reg,
+ struct brw_reg),
const struct brw_reg *dst,
GLuint mask,
const struct brw_reg *arg0);
void emit_alu2(struct brw_compile *p,
- struct brw_instruction *(*func)(struct brw_compile *,
- struct brw_reg,
- struct brw_reg,
- struct brw_reg),
+ int (*func)(struct brw_compile *,
+ struct brw_reg,
+ struct brw_reg,
+ struct brw_reg),
const struct brw_reg *dst,
GLuint mask,
const struct brw_reg *arg0,
diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c
b/src/mesa/drivers/dri/i965/brw_wm_emit.c
index b5a4a4f..c9e3bf6 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c
@@ -506,9 +506,9 @@ void emit_ddxy(struct brw_compile *p,
}
void emit_alu1(struct brw_compile *p,
- struct brw_instruction *(*func)(struct brw_compile *,
- struct brw_reg,
- struct brw_reg),
+ int (*func)(struct brw_compile *,
+ struct brw_reg,
+ struct brw_reg),
const struct brw_reg *dst,
GLuint mask,
const struct brw_reg *arg0)
@@ -530,10 +530,10 @@ void emit_alu1(struct brw_compile *p,
void emit_alu2(struct brw_compile *p,
- struct brw_instruction *(*func)(struct brw_compile *,
- struct brw_reg,
- struct brw_reg,
- struct brw_reg),
+ int (*func)(struct brw_compile *,
+ struct brw_reg,
+ struct brw_reg,
+ struct brw_reg),
const struct brw_reg *dst,
GLuint mask,
const struct brw_reg *arg0,
@@ -1537,7 +1537,7 @@ void emit_fb_write(struct brw_wm_compile *c,
get_element_ud(brw_vec8_grf(1,0), 6),
brw_imm_ud(1<<26));
- jmp = brw_JMPI(p, ip, ip, brw_imm_w(0));
+ jmp = brw_insn_of(p, brw_JMPI(p, ip, ip, brw_imm_w(0)));
{
emit_aa(c, arg1, 2);
fire_fb_write(c, 0, nr, target, eot);
--
1.7.4.4
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