On Tue, 2015-11-17 at 21:54 -0800, Jordan Justen wrote:
> This code will also be usable by the pass to lower shared variables.
>
> Note, that *const_offset is adjusted by setup_buffer_access so it must
> be initialized before calling setup_buffer_access.
>
> v2:
> * Add comment for lower_buffer_
Reviewed-by:; Iago Toral Quiroga
On Tue, 2015-11-17 at 21:54 -0800, Jordan Justen wrote:
> Signed-off-by: Jordan Justen
> Cc: Iago Toral Quiroga
> ---
> src/glsl/lower_ubo_reference.cpp | 64
> +---
> 1 file changed, 34 insertions(+), 30 deletions(-)
>
> d
Reviewed-by: Iago Toral Quiroga
On Tue, 2015-11-17 at 21:55 -0800, Jordan Justen wrote:
> The compiler probably already blocks this earlier on, but we should be
> checking for an SSBO here.
>
> Signed-off-by: Jordan Justen
> Cc: Samuel Iglesias Gonsalvez
> Cc: Iago Toral Quiroga
> ---
> src/
On Tue, 2015-11-17 at 21:55 -0800, Jordan Justen wrote:
> When an atomic function is called, we need to check to see if it is
> for an SSBO variable before lowering it to the SSBO specific intrinsic
> function.
>
> v2:
> * is_in_buffer_block => is_in_shader_storage_block (Iago)
>
> Signed-off-by
On 07.11.2015 12:05, Vivek Kasireddy wrote:
> These flags can be used by the DRI driver to set additional requirements
> such as tiling while creating buffers.
>
> v2: Added a brief comment to explain the rotation orientation.
>
> Cc: Michel Danzer
> Signed-off-by: Vivek Kasireddy
> ---
> incl
On 07.11.2015 12:05, Vivek Kasireddy wrote:
> For certain platforms that support rotated scanout buffers, currently,
> there is no way to create them with the GBM DRI interface. These flags
> will instruct the DRI driver to create the buffer by setting
> additional requirements such as tiling mode.
On Tue, Nov 17, 2015 at 05:30:06PM -0800, Ben Widawsky wrote:
> Background: Prior to Skylake and since Ivybridge Intel hardware has had the
> ability to use a MCS (Multisample Control Surface) as auxiliary data in
> "compression" operations on the surface. This reduces memory bandwidth. This
> har
On Wed, Nov 18, 2015 at 11:10:12AM +0200, Pohjolainen, Topi wrote:
> On Tue, Nov 17, 2015 at 05:30:06PM -0800, Ben Widawsky wrote:
> > Background: Prior to Skylake and since Ivybridge Intel hardware has had the
> > ability to use a MCS (Multisample Control Surface) as auxiliary data in
> > "compres
https://bugs.freedesktop.org/show_bug.cgi?id=92987
Bug ID: 92987
Summary: fails to determine screen refresh rate when rendering
is offloaded
Product: Mesa
Version: unspecified
Hardware: x86-64 (AMD64)
OS: Li
On Tue, Nov 17, 2015 at 05:31:12PM -0800, Ben Widawsky wrote:
> Some of the information originally in this commit message is now in the patch
> before this.
>
> SKL adds compressible render targets and as a result mutates some of the
> programming for fast clears and resolves. There is a new inter
https://bugs.freedesktop.org/show_bug.cgi?id=92987
Stefan Dirsch changed:
What|Removed |Added
Status|NEW |NEEDINFO
--- Comment #1 from Stefan Dirs
https://bugs.freedesktop.org/show_bug.cgi?id=92987
--- Comment #2 from Oliver Neukum ---
(In reply to Stefan Dirsch from comment #1)
> What's wrong with limiting fps to the refresh rate of 60Hz? vblank_mode in
> /etc/drirc (~/.drirc) controls this. It's enabled (=1) by default.
Nothing is wrong
https://bugs.freedesktop.org/show_bug.cgi?id=92987
Oliver Neukum changed:
What|Removed |Added
Status|NEEDINFO|NEW
--
You are receiving this mail beca
https://bugs.freedesktop.org/show_bug.cgi?id=70264
Pekka Paalanen changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
This was only used to implement an unnecessarily restrictive interpretation
of the spec of AMD_performance_monitor. The spec says
A performance monitor consists of a number of hardware and software
counters that can be sampled by the GPU and reported back to the
application.
I guess one cou
Reviewed-by: Samuel Pitoiset
---
src/gallium/include/pipe/p_defines.h | 2 ++
src/mesa/state_tracker/st_cb_perfmon.c | 3 +++
2 files changed, 5 insertions(+)
diff --git a/src/gallium/include/pipe/p_defines.h
b/src/gallium/include/pipe/p_defines.h
index 7f241c8..7ed9f6d 100644
--- a/src/galli
v2 + v3: forgot null-pointer checks (spotted by Samuel Pitoiset)
---
src/mesa/state_tracker/st_cb_perfmon.c | 83 +++---
src/mesa/state_tracker/st_cb_perfmon.h | 6 +++
2 files changed, 82 insertions(+), 7 deletions(-)
diff --git a/src/mesa/state_tracker/st_cb_perfmon
Reviewed-by: Samuel Pitoiset
---
src/gallium/auxiliary/hud/hud_driver_query.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/gallium/auxiliary/hud/hud_driver_query.c
b/src/gallium/auxiliary/hud/hud_driver_query.c
index f14305e..3198ab3 100644
--- a/src/gallium/auxiliary/hud/hud_driver_qu
Previously, when a performance monitor was initialized, an inner loop through
all driver queries with string comparisons for each enabled performance
monitor counter was used. This hurts when a driver exposes lots of queries.
Reviewed-by: Samuel Pitoiset
---
src/mesa/state_tracker/st_cb_perfmon.
Hi everybody,
this is the next iteration of the series, rebased on current master and
with the adjustment to nv50 queries. Please take a look! Samuel, let me know
when you've tested this!
Cheers,
Nicolai
---
gallium/auxiliary/hud/hud_context.c | 24 +-
gallium/auxiliary/hud/hud_driver_qu
Reviewed-by: Samuel Pitoiset
---
src/mesa/state_tracker/st_cb_perfmon.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/src/mesa/state_tracker/st_cb_perfmon.c
b/src/mesa/state_tracker/st_cb_perfmon.c
index 80ff170..ec12eb2 100644
--- a/src/mesa/state_tracker/st_cb_perf
Some drivers (in particular radeon[si], but also freedreno judging from
a quick grep) may want to expose performance counters that cannot be
individually enabled or disabled.
Allow such drivers to mark driver-specific queries as requiring a new
type of batch query object that is used to start and
v2 + v3: be more defensive about allocations
---
src/gallium/auxiliary/hud/hud_context.c | 24 ++-
src/gallium/auxiliary/hud/hud_driver_query.c | 270 +++
src/gallium/auxiliary/hud/hud_private.h | 13 +-
3 files changed, 261 insertions(+), 46 deletions(-)
diff
It is easy enough to pre-determine the required size, and arrays are
generally better behaved especially when they get large.
v2: make sure init_perf_monitor returns true when no counters are active
(spotted by Samuel Pitoiset)
Reviewed-by: Samuel Pitoiset
---
src/mesa/state_tracker/st_cb_perfm
Ben Widawsky writes:
> On Sat, Nov 14, 2015 at 01:43:41PM -0800, Jordan Justen wrote:
>> From: Francisco Jerez
>>
>> It should be possible to use additional L3 configurations other than
>> the ones listed in the tables of validated allocations ("BSpec »
>> 3D-Media-GPGPU Engine » L3 Cache and U
Jordan Justen writes:
> From: Francisco Jerez
>
> Allow for pipelined register writes for gen < 7.
>
> v2:
> * Split from another patch and adjust comment (jljusten)
>
> Reviewed-by: Jordan Justen
> ---
> src/mesa/drivers/dri/i965/intel_extensions.c | 7 +--
> 1 file changed, 5 insertions
https://bugs.freedesktop.org/show_bug.cgi?id=92985
--- Comment #1 from Emil Velikov ---
I'm assuming that this fails as said ar expects to create a non empty archive.
Thus moving the noinst_LTLIBRARIES += libloader_dri3_helper.la into the if
HAVE_DRI3 section should fix things.
Seems that we're
Connor Abbott writes:
> On Tue, Nov 3, 2015 at 8:04 PM, Francisco Jerez wrote:
>> Francisco Jerez writes:
>>
>>> Connor Abbott writes:
>>>
Hi all,
While working on FP64 for i965, there's an issue that I thought of
with the vec4 backend that I'm not sure how to resolve. From
https://bugs.freedesktop.org/show_bug.cgi?id=92985
--- Comment #2 from Martin Peres ---
(In reply to Emil Velikov from comment #1)
> I'm assuming that this fails as said ar expects to create a non empty
> archive.
> Thus moving the noinst_LTLIBRARIES += libloader_dri3_helper.la into the if
> HAV
Hi,
On 13-11-15 19:51, Tom Stellard wrote:
On Fri, Nov 13, 2015 at 02:46:52PM +0100, Hans de Goede wrote:
Hi All,
So as discussed I've started working on a TGSI backend for
llvm to use as a way to get compute going on nouveau (and other gpu-s).
I'm still learning all the ins and outs of llvm
On Wed, Nov 18, 2015 at 03:53:37PM +0100, Hans de Goede wrote:
> Hi,
>
> On 13-11-15 19:51, Tom Stellard wrote:
> > On Fri, Nov 13, 2015 at 02:46:52PM +0100, Hans de Goede wrote:
> >> Hi All,
> >>
> >> So as discussed I've started working on a TGSI backend for
> >> llvm to use as a way to get comp
https://bugs.freedesktop.org/show_bug.cgi?id=92985
--- Comment #3 from Emil Velikov ---
(In reply to Martin Peres from comment #2)
> (In reply to Emil Velikov from comment #1)
> > I'm assuming that this fails as said ar expects to create a non empty
> > archive.
> > Thus moving the noinst_LTLIBR
Matt Turner writes:
> Since the types of the expression were
>
>bool ? src_reg : (bool ? brw_reg : brw_reg)
>
> the result of the second (nested) ternary would be implicitly
> converted to a src_reg by the src_reg(struct brw_reg) constructor. I.e.,
>
>bool ? src_reg : src_reg(bool ? brw_r
From: Ian Romanick
There are no shaders, so it doesn't even make sense to expose the
extension.
Signed-off-by: Ian Romanick
Cc: Nanley Chery
---
src/mesa/main/extensions_table.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/main/extensions_table.h b/src/mesa/mai
Hi Tom,
Please flip the order of the patches and drop the now patch 1/2 from
the stable queue.
On 16 November 2015 at 20:03, Tom Stellard wrote:
> The compiler has more information and is able to optimize the bits
> it sets in these registers.
>
> CC:
> ---
> src/gallium/drivers/radeonsi/si_co
From: Ian Romanick
builtin_functions.cpp:5289:52: warning: unused parameter 'num_arguments'
[-Wunused-parameter]
unsigned num_arguments,
^
builtin_functions.cpp:5290:52: warning: unused parameter 'flag
The queries_suspended_for_flush flag is redundant because suspended queries
are not removed from their respective linked list.
---
src/gallium/drivers/radeon/r600_pipe_common.c | 13 ++---
src/gallium/drivers/radeon/r600_pipe_common.h | 2 --
2 files changed, 6 insertions(+), 9 deletions(
From: Ian Romanick
I think the intention was to mark the "this" parameter as const, but
const goes on the other end to do that.
In file included from glsl_symbol_table.cpp:26:0:
ast.h:339:35: warning: type qualifiers ignored on function return type
[-Wignored-qualifiers]
const bool is_singl
From: Ian Romanick
Apparently, this has been a bug since 2010 (c30f6e5d).
Also use ARRAY_SIZE instead of open coding it.
Signed-off-by: Ian Romanick
Cc: Kenneth Graunke
Cc: mesa-sta...@lists.freedesktop.org
---
src/glsl/ir.cpp | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --g
Reviewed-by: Ilia Mirkin
On Wed, Nov 18, 2015 at 12:44 PM, Ian Romanick wrote:
> From: Ian Romanick
>
> builtin_functions.cpp:5289:52: warning: unused parameter 'num_arguments'
> [-Wunused-parameter]
>unsigned num_arguments,
>
On Wednesday, November 18, 2015 09:44:34 AM Ian Romanick wrote:
> From: Ian Romanick
>
> Apparently, this has been a bug since 2010 (c30f6e5d).
>
> Also use ARRAY_SIZE instead of open coding it.
>
> Signed-off-by: Ian Romanick
> Cc: Kenneth Graunke
> Cc: mesa-sta...@lists.freedesktop.org
> --
On Sat, Nov 14, 2015 at 6:59 PM, Connor Abbott wrote:
> Not sure how this wasn't already caught by valgrind, but it fixes an
> issue with the vectorizer.
Ugh... I'm getting tired of fixing these bugs.
> Signed-off-by: Connor Abbott
Both are
Cc: "11.0"
Reviewed-by: Jason Ekstrand
> ---
> s
On Tue, Nov 17, 2015 at 11:41 PM, Connor Abbott wrote:
> On Mon, Nov 16, 2015 at 11:00 AM, Jason Ekstrand wrote:
>> On Sat, Nov 14, 2015 at 6:59 PM, Connor Abbott wrote:
>>> Shader-db results on bdw with INTEL_DEBUG=vec4:
>>>
>>> total instructions in shared programs: 1634044 -> 1612936 (-1.29%)
On Tue 17 Nov 2015, Ben Widawsky wrote:
> Background: Prior to Skylake and since Ivybridge Intel hardware has had the
> ability to use a MCS (Multisample Control Surface) as auxiliary data in
> "compression" operations on the surface. This reduces memory bandwidth. This
> hardware was either used
Hi Tim,
I have no objections against getting this merged, although here are a
couple of things that should be sorted. Some of these are just
reiteration from others:
- First and foremost - please base your work against master. Mesa,
alike most other open-source projects, tries to keep features o
On Tue, Nov 17, 2015 at 10:35 PM, Oded Gabbay wrote:
> This patch disables the use of VSX instructions, as they cause some
> piglit tests to fail
>
> For more details, see: https://llvm.org/bugs/show_bug.cgi?id=25503#c7
>
> With this patch, ppc64le reaches parity with x86-64 as far as piglit test
On 18/11/15 18:52, Oded Gabbay wrote:
On Tue, Nov 17, 2015 at 10:35 PM, Oded Gabbay wrote:
This patch disables the use of VSX instructions, as they cause some
piglit tests to fail
For more details, see: https://llvm.org/bugs/show_bug.cgi?id=25503#c7
With this patch, ppc64le reaches parity wit
Am 17.11.2015 um 21:35 schrieb Oded Gabbay:
> This patch disables the use of VSX instructions, as they cause some
> piglit tests to fail
>
> For more details, see: https://llvm.org/bugs/show_bug.cgi?id=25503#c7
>
> With this patch, ppc64le reaches parity with x86-64 as far as piglit test
> suite
Hi Tapani,
On 28 October 2015 at 13:27, Tapani Pälli wrote:
> On 10/27/2015 06:42 PM, Ian Romanick wrote:
>>
>> On 10/27/2015 12:11 AM, Tapani Pälli wrote:
>>>
>>> Fixes following failing dEQP test:
>>> dEQP-GLES3.functional.fbo.api.attachment_query_empty_fbo
>>>
>>> Signed-off-by: Tapani Päl
Hi Ilia,
On 11 November 2015 at 00:28, Ilia Mirkin wrote:
> On Tue, Nov 10, 2015 at 7:24 PM, Connor Abbott wrote:
>> On Tue, Nov 10, 2015 at 7:02 PM, Ilia Mirkin wrote:
>>> On Tue, Nov 10, 2015 at 6:44 PM, Eric Anholt wrote:
Ilia Mirkin writes:
> In nv50, and in the python scrip
On Wed, Nov 18, 2015 at 2:03 PM, Emil Velikov wrote:
> Hi Ilia,
>
> On 11 November 2015 at 00:28, Ilia Mirkin wrote:
>> On Tue, Nov 10, 2015 at 7:24 PM, Connor Abbott wrote:
>>> On Tue, Nov 10, 2015 at 7:02 PM, Ilia Mirkin wrote:
On Tue, Nov 10, 2015 at 6:44 PM, Eric Anholt wrote:
> I
On Sat, Nov 14, 2015 at 6:59 PM, Connor Abbott wrote:
> This effectively does the opposite of nir_lower_alus_to_scalar, trying
> to combine per-component ALU operations with the same sources but
> different swizzles into one larger ALU operation. It uses a similar
> model as CSE, where we do a dep
On 11/18/2015 10:05 AM, Kenneth Graunke wrote:
> On Wednesday, November 18, 2015 09:44:34 AM Ian Romanick wrote:
>> From: Ian Romanick
>>
>> Apparently, this has been a bug since 2010 (c30f6e5d).
>>
>> Also use ARRAY_SIZE instead of open coding it.
>>
>> Signed-off-by: Ian Romanick
>> Cc: Kenneth
Reviwed-by: Jason Ekstrand
On Wed, Nov 18, 2015 at 9:44 AM, Ian Romanick wrote:
> From: Ian Romanick
>
> There are no shaders, so it doesn't even make sense to expose the
> extension.
>
> Signed-off-by: Ian Romanick
> Cc: Nanley Chery
> ---
> src/mesa/main/extensions_table.h | 2 +-
> 1 file
On Wed, Nov 18, 2015 at 11:50 AM, Jason Ekstrand wrote:
> Reviwed-by: Jason Ekstrand
idr: Please fix Jason's typo when you amend the patch.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
On Wed, Nov 18, 2015 at 2:06 PM, Ilia Mirkin wrote:
> On Wed, Nov 18, 2015 at 2:03 PM, Emil Velikov
> wrote:
>> Hi Ilia,
>>
>> On 11 November 2015 at 00:28, Ilia Mirkin wrote:
>>> On Tue, Nov 10, 2015 at 7:24 PM, Connor Abbott wrote:
On Tue, Nov 10, 2015 at 7:02 PM, Ilia Mirkin wrote:
>>
From: Nanley Chery
Help developers understand the table's organization.
Suggested-by: Jason Ekstrand
Signed-off-by: Nanley Chery
---
src/mesa/main/extensions_table.h | 17 +
1 file changed, 17 insertions(+)
diff --git a/src/mesa/main/extensions_table.h b/src/mesa/main/extensi
Hi Nanley,
On 18 November 2015 at 20:29, Nanley Chery wrote:
> From: Nanley Chery
>
> Help developers understand the table's organization.
>
> Suggested-by: Jason Ekstrand
> Signed-off-by: Nanley Chery
Can you bring back the comments that were in here, please. They might
have cause issues with
From: Rob Clark
Reference counting (which is introduced in a subsequent patch) basically
should only be done on root nodes in the ralloc tree. In particular,
having multiple threads calling in to ralloc for the same graph will not
work.
Whereas reference-counting of shaders will be a useful thi
From: Rob Clark
For gallium, at least, we'll need this to manage shader's lifetimes,
since in some cases both the driver and the state tracker will need
to hold on to a reference for variant managing.
Use nir_shader_mutable() before doing any IR opt/lowering/etc, to
ensure you are not modifying
On Tue, Nov 10, 2015 at 12:48 AM, Kenneth Graunke wrote:
> I've been carrying around a patch to do this for the last few months,
> and it's been exceedingly useful for debugging GS and tessellation
> problems. I've caught lots of bugs by inspecting the interface
> expectations of two adjacent sta
On Wed, 2015-11-18 at 09:44 -0800, Ian Romanick wrote:
> From: Ian Romanick
>
> I think the intention was to mark the "this" parameter as const, but
> const goes on the other end to do that.
>
> In file included from glsl_symbol_table.cpp:26:0:
> ast.h:339:35: warning: type qualifiers ignored on
On Sat, Nov 7, 2015 at 9:04 PM, Kenneth Graunke wrote:
> This allows arbitrary non-constant indices on GS input arrays,
> both for the vertex index, and any array offsets beyond that.
>
> All indirects are handled via the pull model. We could potentially
> handle indirect addressing of pushed dat
On Tue, Nov 17, 2015 at 02:20:28PM -0800, Ben Widawsky wrote:
> On Tue, Nov 17, 2015 at 11:40:53AM -0800, Sarah Sharp wrote:
> > Add PCI IDs for the Intel Kabylake platforms. The IDs are taken
> > directly from the Linux kernel patches, which are under review:
> >
> > http://lists.freedesktop.org
On Wed, Nov 18, 2015 at 4:54 PM, Sarah Sharp
wrote:
>> There's not really a consensus I guess, but most people do leave the version
>> information in the final commit message.
>
> I personally feel like that's leaving boredom doodles on a final
> architectural drawing. If people want to know the b
From: Rob Clark
Kind of a handy function. And I'll what it available outside of i965
for common nir-pass helpers.
Signed-off-by: Rob Clark
---
src/mesa/drivers/dri/i965/brw_context.c | 5 +++--
src/mesa/drivers/dri/i965/brw_nir.c | 4 +++-
src/mesa/drivers/dri/i965/brw_shader.cpp | 3
From: Rob Clark
Note these are a bit uglier, due to avoidance of GNU C extensions. But
drivers which do not need to be built with compilers that don't support
the extension can wrap these macros with their own.
Signed-off-by: Rob Clark
---
src/glsl/nir/nir.h | 35
The region fields are unioned with the immediate storage.
---
src/mesa/drivers/dri/i965/brw_reg.h | 6 --
1 file changed, 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_reg.h
b/src/mesa/drivers/dri/i965/brw_reg.h
index 3da83b4..759bd93 100644
--- a/src/mesa/drivers/dri/i965/brw_re
---
This fails... for reasons I cannot determine. Can anyone spot what's wrong?
I'm okay with just committing the v1 of 2/2 and not blocking this feature on
this optimization.
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 43
1 file changed, 43 insertions(+)
diff -
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 3 +++
src/mesa/drivers/dri/i965/brw_reg.h| 9 +
2 files changed, 12 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index e5a286a..78c10e9 100644
-
On Wed, Nov 18, 2015 at 2:25 PM, Matt Turner wrote:
> ---
> This fails... for reasons I cannot determine. Can anyone spot what's wrong?
Ilia identified the problem in 10 seconds -- I need to NOT the pixel
mask. A set bit in the mask means the channel is enabled, and that's
the opposite of what gl
On Wed, Nov 18, 2015 at 1:54 PM, Sarah Sharp
wrote:
> On Tue, Nov 17, 2015 at 02:20:28PM -0800, Ben Widawsky wrote:
>> On Tue, Nov 17, 2015 at 11:40:53AM -0800, Sarah Sharp wrote:
>> > Add PCI IDs for the Intel Kabylake platforms. The IDs are taken
>> > directly from the Linux kernel patches, whi
On Wed, Nov 18, 2015 at 12:33 PM, Emil Velikov
wrote:
> Hi Nanley,
>
> On 18 November 2015 at 20:29, Nanley Chery wrote:
> > From: Nanley Chery
> >
> > Help developers understand the table's organization.
> >
> > Suggested-by: Jason Ekstrand
> > Signed-off-by: Nanley Chery
> Can you bring bac
From: Nanley Chery
Suggested-by: Marek Olšák
Suggested-by: Emil Velikov
Signed-off-by: Nanley Chery
---
src/mesa/main/extensions_table.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/main/extensions_table.h b/src/mesa/main/extensions_table.h
index d12fd9f..87f
On Wed, Oct 14, 2015 at 5:11 AM, Michel Thierry
wrote:
> On 10/14/2015 8:19 AM, Daniel Vetter wrote:
>>
>> On Tue, Oct 13, 2015 at 02:51:36PM -0700, Kristian Høgsberg wrote:
>>>
>>> On Tue, Oct 13, 2015 at 7:55 AM, Michel Thierry
>>> wrote:
On 10/13/2015 3:13 PM, Emil Velikov wrote:
>>>
From: Nanley Chery
Enable developers to know if the table's alphabetical sorting
is maintained or lost.
Signed-off-by: Nanley Chery
---
src/mesa/main/extensions.h | 1 +
src/mesa/main/tests/Makefile.am | 1 +
src/mesa/main/tests/mesa_extensions.cpp | 47 +
From: Nanley Chery
Make it easier to determine where to add new extensions.
Performed with the vim sort command.
Signed-off-by: Nanley Chery
---
src/mesa/main/extensions_table.h | 173 +--
1 file changed, 92 insertions(+), 81 deletions(-)
diff --git a/src/m
In most cases (when the negate is copy propagated and the MOV removed),
this is two instructions on Gen >= 8 and only two instructions on
earlier platforms -- and it doesn't use the flag register.
---
Thanks Ilia!
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 52
1 f
Why have the count as an entry in the enum? Can't you just do
ARRAY_SIZE(_mesa_extension_table) ?
On Wed, Nov 18, 2015 at 6:01 PM, Nanley Chery wrote:
> From: Nanley Chery
>
> Enable developers to know if the table's alphabetical sorting
> is maintained or lost.
>
> Signed-off-by: Nanley Chery
On Wed, Nov 18, 2015 at 6:06 PM, Matt Turner wrote:
> In most cases (when the negate is copy propagated and the MOV removed),
> this is two instructions on Gen >= 8 and only two instructions on
> earlier platforms -- and it doesn't use the flag register.
> ---
> Thanks Ilia!
>
> src/mesa/drivers/
On Wed, Nov 18, 2015 at 3:09 PM, Ilia Mirkin wrote:
> On Wed, Nov 18, 2015 at 6:06 PM, Matt Turner wrote:
>> In most cases (when the negate is copy propagated and the MOV removed),
>> this is two instructions on Gen >= 8 and only two instructions on
>> earlier platforms -- and it doesn't use the
On Wed, Nov 18, 2015 at 3:07 PM, Ilia Mirkin wrote:
> Why have the count as an entry in the enum? Can't you just do
> ARRAY_SIZE(_mesa_extension_table) ?
>
>
The compiler doesn't know the size of the array by just looking at the
header. To use ARRAY_SIZE, I'd have to modify the declaration of
_me
On Tue, Nov 17, 2015 at 9:54 PM, Jordan Justen
wrote:
> From: Francisco Jerez
>
> This calculates a rather conservative partitioning of the L3 cache
> based on the shaders currently bound to the pipeline and whether they
> use SLM, atomics, images or scratch space. The result is intended to
> be
From: Ian Romanick
This is the NIR analog to GLSL IR ir_samples_identical. However, the
NIR has an extra source. This is a fake sample index with a type
nir_tex_src_ms_index. This enables backends to (likely) share more code
with the existing nir_texop_txf_ms implementation.
Signed-off-by: Ia
From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 1 +
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 16
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 1 +
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 11 +++
From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/mesa/main/extensions_table.h | 1 +
src/mesa/main/mtypes.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/mesa/main/extensions_table.h b/src/mesa/main/extensions_table.h
index 8685a89..87b6645 100644
--- a/src/mesa/main
This patch series implements a new GL extension,
EXT_shader_samples_identical. This extension allows shaders to
determine when all of the samples in a particular texel are the same.
This takes advantage of the way compressed multisample surfaces are
stored on modern Intel and AMD hardware. This e
From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/glsl/glcpp/glcpp-parse.y| 3 +++
src/glsl/glsl_parser_extras.cpp | 1 +
src/glsl/glsl_parser_extras.h | 2 ++
3 files changed, 6 insertions(+)
diff --git a/src/glsl/glcpp/glcpp-parse.y b/src/glsl/glcpp/glcpp-parse.y
index 6aa7abe..8f
From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/glsl/ir.cpp| 6 +-
src/glsl/ir.h | 2 ++
src/glsl/ir_clone.cpp | 1 +
src/glsl/ir_equals.cpp | 1 +
src/glsl/ir_hv_accept.cpp
From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 16 +++-
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index cdd470b..1f71f66 100644
---
From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/glsl/builtin_functions.cpp | 44 ++
1 file changed, 44 insertions(+)
diff --git a/src/glsl/builtin_functions.cpp b/src/glsl/builtin_functions.cpp
index eb438d9..db01810 100644
--- a/src/glsl/builtin_
On Wed, Nov 18, 2015 at 3:01 PM, Nanley Chery wrote:
> From: Nanley Chery
>
> Make it easier to determine where to add new extensions.
> Performed with the vim sort command.
Well, I think I'm obligated to review such a patch :)
> Signed-off-by: Nanley Chery
> ---
> src/mesa/main/extensions_ta
From: Ian Romanick
Signed-off-by: Ian Romanick
Cc: "Chris Forbes"
---
docs/specs/EXT_shader_samples_identical.txt | 174
1 file changed, 174 insertions(+)
create mode 100644 docs/specs/EXT_shader_samples_identical.txt
diff --git a/docs/specs/EXT_shader_samples_id
On Wed, Nov 18, 2015 at 11:10:12AM +0200, Pohjolainen, Topi wrote:
> On Tue, Nov 17, 2015 at 05:30:06PM -0800, Ben Widawsky wrote:
> > Background: Prior to Skylake and since Ivybridge Intel hardware has had the
> > ability to use a MCS (Multisample Control Surface) as auxiliary data in
> > "compres
On Wed, Nov 18, 2015 at 10:28:27AM -0800, Chad Versace wrote:
> On Tue 17 Nov 2015, Ben Widawsky wrote:
> > Background: Prior to Skylake and since Ivybridge Intel hardware has had the
> > ability to use a MCS (Multisample Control Surface) as auxiliary data in
> > "compression" operations on the sur
On Wed, Nov 18, 2015 at 3:01 PM, Nanley Chery wrote:
> From: Nanley Chery
>
> Enable developers to know if the table's alphabetical sorting
> is maintained or lost.
My hero.
> Signed-off-by: Nanley Chery
> ---
> src/mesa/main/extensions.h | 1 +
> src/mesa/main/tests/Makefile.am
It lives! Thanks for picking this up, Ian.
Had a very brief look at the series as it arrived, looks good; will try to
do a real review later today.
- Chris
On Nov 19, 2015 12:47 PM, "Ian Romanick" wrote:
> This patch series implements a new GL extension,
> EXT_shader_samples_identical. This ex
The hardware can actually generates vertexid when vertices come from
a client-side buffer like when glDrawElements is used.
This doesn't fix (or break) any piglit tests but it improves the
previous attempt of Ilia (c830d19 "nv50: avoid using inline vertex
data submit when gl_VertexID is used")
Th
On Wednesday, November 18, 2015 03:46:54 PM Ian Romanick wrote:
> From: Ian Romanick
>
> Signed-off-by: Ian Romanick
> ---
> src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 1 +
> src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 16
> src/mesa/drivers/dri/i965/brw_vec4_nir.cp
On Wednesday, November 18, 2015 03:46:53 PM Ian Romanick wrote:
> From: Ian Romanick
>
> Signed-off-by: Ian Romanick
> ---
> src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 16 +++-
> 1 file changed, 7 insertions(+), 9 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.c
1 - 100 of 152 matches
Mail list logo
