Re: [Mesa-dev] [PATCH 6/6] radeonsi: always use async compiles when creating shader/compute states

For the series: Reviewed-by: Marek Olšák Marek On Sun, Oct 22, 2017 at 8:45 PM, Nicolai Hähnle wrote: > From: Nicolai Hähnle > > With Gallium threaded contexts, creating shader/compute states is > effectively a screen operation, so we should not use context state. > > In particular, this allo

Re: [Mesa-dev] [PATCH 00/21] anv: Do cross-stage link optimizations

On Sat, Oct 28, 2017 at 11:36 AM, Jason Ekstrand wrote: > This series adds support for cross-stage optimizations in anv. There are a > few patches from Jordan's shader cache series in here that I wanted because > they made my life easier. There are also three patches CCd to stable to > fix a bu

Re: [Mesa-dev] [PATCH 01/21] intel/compiler: Add union types for prog_data and prog_key stages

Thanks On October 28, 2017 15:15:48 Jordan Justen wrote: In case you push this before the shader cache, in my current i965-shader-cache branch, 1 & 2 have an r-b from you, and patch 1 has an comments requested by Ken. -Jordan On 2017-10-28 11:36:09, Jason Ekstrand wrote: From: Jordan Juste

Re: [Mesa-dev] [PATCH 2/7] nir: add varying component packing helpers

On 29/10/17 02:21, Jason Ekstrand wrote: On October 28, 2017 07:15:10 Bas Nieuwenhuizen wrote: On Mon, Oct 23, 2017 at 2:10 AM, Timothy Arceri wrote: ---  src/compiler/nir/nir.h |   2 +  src/compiler/nir/nir_linking_helpers.c | 235 +  2 file

[Mesa-dev] [Bug 100316] Linking GLSL 1.30 shaders with invariant and deprecated variables triggers an 'mismatching invariant qualifiers' error

https://bugs.freedesktop.org/show_bug.cgi?id=100316 Daniel Gibson changed: What|Removed |Added CC||metalcae...@gmail.com -- You are recei

[Mesa-dev] [Bug 100316] Linking GLSL 1.30 shaders with invariant and deprecated variables triggers an 'mismatching invariant qualifiers' error

https://bugs.freedesktop.org/show_bug.cgi?id=100316 --- Comment #1 from Daniel Gibson --- I ran into the same bug, on Ubuntu 17.04 with both Mesa 17.0.7-0ubuntu0.17.04.1 and 17.2.2+git20171019+17.2.23c08dab-0ubuntu0ricotz~17.04.1 (from the xorg-edgers ppa). I have observed this bug both with Inte

Re: [Mesa-dev] [PATCH v3] radv: Implement VK_AMD_shader_info

I fixed the LDS reporting (lds_size is what is in the reg, we need a multiplier), and pushed this. Thanks. On Fri, Oct 27, 2017 at 3:25 PM, Alex Smith wrote: > This allows an app to query shader statistics and get a disassembly of > a shader. RenderDoc git has support for it, so this allows you t

Re: [Mesa-dev] [PATCH 01/21] intel/compiler: Add union types for prog_data and prog_key stages

In case you push this before the shader cache, in my current i965-shader-cache branch, 1 & 2 have an r-b from you, and patch 1 has an comments requested by Ken. -Jordan On 2017-10-28 11:36:09, Jason Ekstrand wrote: > From: Jordan Justen > > Signed-off-by: Jordan Justen > --- > src/intel/compi

Re: [Mesa-dev] Mesa 17.2.4 release candidate

On Fri, 2017-10-27 at 14:14 -0400, Ilia Mirkin wrote: > On Fri, Oct 27, 2017 at 1:43 PM, Andres Gomez wrote: > > Rejected (6) > > > > > > Ilia Mirkin (1): > > glsl: fix derived cs variables > > > > Reason: Commit is too big for stable at this point. > > The issue it fixes in

Re: [Mesa-dev] [PATCH 4/4] i965: Only set key->high_quality_derivatives when it matters.

On Saturday, October 28, 2017 11:08:29 AM PDT Jason Ekstrand wrote: > Have you seen this matter somewhere? It seems like a reasonable thing to > do none the less. 3 and 4 are > > Reviewed-by: Jason Ekstrand Yeah, the Aztec Ruins GL version hits this on almost all of its fragment shaders. Unfo

Re: [Mesa-dev] [PATCH] etnaviv: make use of TEXTURE_TYPE_1D

On Thu, Oct 26, 2017 at 04:16:31PM +0200, Christian Gmeiner wrote: > I have no problem to postpone this patch until I have my farm up and > get the first results. Alternatively, I'd say just disable this for !HALTI0 for now, revert to the old behavior in that case, then someone who is able to tes

[Mesa-dev] [PATCH 14/21] anv/pipeline: Compile to NIR in compile_graphics

This pulls the SPIR-V to NIR step out into common code. --- src/intel/vulkan/anv_pipeline.c | 216 +--- 1 file changed, 91 insertions(+), 125 deletions(-) diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index cfec73d..0f28245 1006

[Mesa-dev] [PATCH 18/21] intel/nir: Break the linking code into a helper in brw_nir.c

Cc: mesa-sta...@lists.freedesktop.org --- src/intel/compiler/brw_nir.c | 32 src/intel/compiler/brw_nir.h | 4 src/mesa/drivers/dri/i965/brw_link.cpp | 38 -- 3 files changed, 40 insertions(+), 34 deletions(-)

[Mesa-dev] [PATCH 16/21] anv/pipeline: Pull most of the anv_pipeline_compile_* into common code

This leaves us with a series of little anv_pipeline_compile_* functions which each take a compiler object, a mem_ctx, the stage to compile, and the previous stage for VUE linking purposes. Some of them do interesting things but most are little more than wrappers around brw_compile_*. --- src/inte

[Mesa-dev] [PATCH 19/21] intel/nir: Use the correct indirect lowering masks in link_shaders

Previously, if we were linking a vec4 VS with a SIMD8/16 FS, we wouldn't lower indirects on the fragment shader which is wrong. Instead of using a single indirect mask, take advantage of our new little helper. Cc: mesa-sta...@lists.freedesktop.org --- src/intel/compiler/brw_nir.c | 10 --

[Mesa-dev] [PATCH 21/21] anv/pipeline: Do cross-stage linking optimizations

This appears to help the Aztec Ruins benchmark by about 2% on my Kaby Lake gt2 laptop. --- src/intel/vulkan/anv_pipeline.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index b9b08f2..5f66c3a 100644 --- a/src/inte

[Mesa-dev] [PATCH 20/21] nir/lower_indirect: Bail early if modes == 0

There's no point in walking the program if 100% if we're never going to actually lower anything. --- src/compiler/nir/nir_lower_indirect_derefs.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/compiler/nir/nir_lower_indirect_derefs.c b/src/compiler/nir/nir_lower_indirect_derefs.c inde

[Mesa-dev] [PATCH 11/21] anv/pipeline: Pull shader compilation out into a helper.

--- src/intel/vulkan/anv_pipeline.c | 209 +--- 1 file changed, 111 insertions(+), 98 deletions(-) diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index ba0ffd7..ec14c73 100644 --- a/src/intel/vulkan/anv_pipeline.c +++ b/src/intel

[Mesa-dev] [PATCH 17/21] intel/nir: Add a helper for getting the NoIndirect mask

Cc: mesa-sta...@lists.freedesktop.org --- src/intel/compiler/brw_nir.c | 33 +++-- 1 file changed, 19 insertions(+), 14 deletions(-) diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index e5ff6de..2d4ab50 100644 --- a/src/intel/compiler/brw_nir.

[Mesa-dev] [PATCH 08/21] anv/pipeline: Populate keys up-front

Instead of having each anv_pipeline_compile_* function populate the shader key, make it part of the anv_pipeline_stage struct and fill it out up-front. --- src/intel/vulkan/anv_pipeline.c | 113 +--- 1 file changed, 59 insertions(+), 54 deletions(-) diff --git

[Mesa-dev] [PATCH 10/21] anv/pipeline: Call anv_pipeline_compile_* in a loop

--- src/intel/vulkan/anv_pipeline.c | 51 ++--- 1 file changed, 27 insertions(+), 24 deletions(-) diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index e6c4955..ba0ffd7 100644 --- a/src/intel/vulkan/anv_pipeline.c +++ b/src/intel/

[Mesa-dev] [PATCH 15/21] anv/pipeline: Add a separate "link" stage

This breaks compilation up a bit into "link" and "compile". In the "link" stage, new anv_pipeline_link_* helpers are called which are responsible for setting up the binding table and doing anything needed to properly link with the next stage in the pipeline if one exists. They are called in revers

[Mesa-dev] [PATCH 13/21] anv/pipeline: Recompile all shaders if any are missing from the cache

--- src/intel/vulkan/anv_pipeline.c | 41 + 1 file changed, 37 insertions(+), 4 deletions(-) diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index 0e58f83..cfec73d 100644 --- a/src/intel/vulkan/anv_pipeline.c +++ b/src/intel/v

[Mesa-dev] [PATCH 09/21] anv/pipeline: Hash the entire pipeline in one go

Instead of hashing each stage separately (and TES and TCS together), we hash the entire pipeline. This means we'll get fewer cache hits if they, for instance, re-use the same VS over and over again but it also means we can now safely do cross-stage optimizations. --- src/intel/vulkan/anv_pipeline

[Mesa-dev] [PATCH 07/21] anv/pipline: Add a helper struct for per-stage info

--- src/intel/vulkan/anv_pipeline.c | 170 +--- src/intel/vulkan/anv_private.h | 2 +- 2 files changed, 74 insertions(+), 98 deletions(-) diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index 8318dea..311bd91 100644 --- a/src/i

[Mesa-dev] [PATCH 12/21] anv/pipeline: Drop anv_pipeline_add_compiled_stage

We can set active_stages much more directly and then it's just candy around setting pipeline->stages[stage]. --- src/intel/vulkan/anv_pipeline.c | 30 -- src/intel/vulkan/genX_pipeline.c | 2 -- 2 files changed, 12 insertions(+), 20 deletions(-) diff --git a/src/inte

[Mesa-dev] [PATCH 04/21] intel/compiler: Remove final_program_size from brw_compile_*

From: Jordan Justen The caller can now use brw_stage_prog_data::program_size which is set by the brw_compile_* functions. Cc: Jason Ekstrand Signed-off-by: Jordan Justen Reviewed-by: Jason Ekstrand --- src/intel/blorp/blorp.c| 10 -- src/intel/blorp/blorp_blit.c

[Mesa-dev] [PATCH 00/21] anv: Do cross-stage link optimizations

This series adds support for cross-stage optimizations in anv. There are a few patches from Jordan's shader cache series in here that I wanted because they made my life easier. There are also three patches CCd to stable to fix a but in the i965 cross-stage NIR linking which, as as side-effect, ex

[Mesa-dev] [PATCH 06/21] anv/pipeline: Add populate_tcs/tes_key helpers

They don't really do anything interesting, but it's more consistent this way. --- src/intel/vulkan/anv_pipeline.c | 28 +--- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index 613cfca..8318d

[Mesa-dev] [PATCH 05/21] anv/pipeline: Rework the parameters to populate_wm_prog_key

--- src/intel/vulkan/anv_pipeline.c | 42 ++--- 1 file changed, 23 insertions(+), 19 deletions(-) diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index 907b24a..613cfca 100644 --- a/src/intel/vulkan/anv_pipeline.c +++ b/src/intel/

[Mesa-dev] [PATCH 02/21] intel/compiler: Add functions to get prog_data and prog_key sizes for a stage

From: Jordan Justen Signed-off-by: Jordan Justen Reviewed-by: Kenneth Graunke --- src/intel/compiler/brw_compiler.c | 36 src/intel/compiler/brw_compiler.h | 6 ++ 2 files changed, 42 insertions(+) diff --git a/src/intel/compiler/brw_compiler.c b/src

[Mesa-dev] [PATCH 01/21] intel/compiler: Add union types for prog_data and prog_key stages

From: Jordan Justen Signed-off-by: Jordan Justen --- src/intel/compiler/brw_compiler.h | 20 1 file changed, 20 insertions(+) diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h index 014202d..3e0756a 100644 --- a/src/intel/compiler/brw_comp

[Mesa-dev] [PATCH 03/21] intel/compiler: add new field for storing program size

From: Carl Worth This will be used by the on disk shader cache. v2: * Set in brw_compile_* rather than brw_codegen_*. (Jason) Signed-off-by: Timothy Arceri [jordan.l.jus...@intel.com: Only add to brw_stage_prog_data] Signed-off-by: Jordan Justen Reviewed-by: Jason Ekstrand --- src/intel/co

Re: [Mesa-dev] [PATCH v2 0/3] Fix for PerVertexValidation CTS test

On Friday, October 27, 2017 12:28:16 PM PDT Neil Roberts wrote: > Hi, > > Here is a v2 of Eduardo’s patches to fix the PerVertexValidation CTS > test. They were originally posted here: > > https://lists.freedesktop.org/archives/mesa-dev/2017-March/146667.html Actually, they're even older than th

Re: [Mesa-dev] [PATCH 4/4] i965: Only set key->high_quality_derivatives when it matters.

Have you seen this matter somewhere? It seems like a reasonable thing to do none the less. 3 and 4 are Reviewed-by: Jason Ekstrand On Sat, Oct 28, 2017 at 10:32 AM, Kenneth Graunke wrote: > This avoids recompiles for shaders that don't use explicit derivatives > when ctx->Hint.FragmentShader

Re: [Mesa-dev] [PATCH 2/4] i965: Update brw_wm_debug_recompile() for newer key entries.

Acked-by: Jason Ekstrand On Sat, Oct 28, 2017 at 10:32 AM, Kenneth Graunke wrote: > Also, reorder them to match the structure's field order, to make it > easier to check that they're all present. > --- > src/mesa/drivers/dri/i965/brw_wm.c | 19 ++- > 1 file changed, 14 insertio

Re: [Mesa-dev] [PATCH 1/4] i965: Delete brw_wm_prog_key::drawable_height.

Yes, Please! Reviewed-by: Jason Ekstrand On Sat, Oct 28, 2017 at 10:32 AM, Kenneth Graunke wrote: > This has been unused since we switched to nir_lower_wpos_ytransform. > --- > src/intel/compiler/brw_compiler.h | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/src/intel/compiler/brw_com

[Mesa-dev] [PATCH 3/4] nir: Make nir_gather_info collect a uses_fddx_fddy flag.

i965 turns fddx/fddy into their coarse/fine variants based on the ctx->Hint.FragmentShaderDerivative setting. It needs to know whether this can impact a shader in order to better guess NOS settings. --- src/compiler/nir/nir_gather_info.c | 16 src/compiler/shader_info.h |

[Mesa-dev] [PATCH 4/4] i965: Only set key->high_quality_derivatives when it matters.

This avoids recompiles for shaders that don't use explicit derivatives when ctx->Hint.FragmentShaderDerivative == GL_NICEST. --- src/mesa/drivers/dri/i965/brw_wm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c index ad1

[Mesa-dev] [PATCH 1/4] i965: Delete brw_wm_prog_key::drawable_height.

This has been unused since we switched to nir_lower_wpos_ytransform. --- src/intel/compiler/brw_compiler.h | 1 - 1 file changed, 1 deletion(-) diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h index 6a330537a5b..17615c6dd9f 100644 --- a/src/intel/compiler/brw_co

[Mesa-dev] [PATCH 2/4] i965: Update brw_wm_debug_recompile() for newer key entries.

Also, reorder them to match the structure's field order, to make it easier to check that they're all present. --- src/mesa/drivers/dri/i965/brw_wm.c | 19 ++- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i

Re: [Mesa-dev] [PATCH] etnaviv: add ext_texture_srgb support

On Sat, Oct 28, 2017 at 05:24:58PM +0200, Christian Gmeiner wrote: > Following piglits are passing: > - glean@texture_srgb > - spec@ext_texture_srgb@fbo-srgb > - spec@ext_texture_srgb@tex-srgb > - spec@ext_texture_srgb@texwrap formats > - spec@ext_texture_srgb@texwrap formats-s3tc > > Btw. th

[Mesa-dev] [PATCH] etnaviv: add ext_texture_srgb support

Following piglits are passing: - glean@texture_srgb - spec@ext_texture_srgb@fbo-srgb - spec@ext_texture_srgb@tex-srgb - spec@ext_texture_srgb@texwrap formats - spec@ext_texture_srgb@texwrap formats-s3tc Btw. this enables GL 2.1 :-) Signed-off-by: Christian Gmeiner --- src/gallium/drivers/e

Re: [Mesa-dev] [PATCH 2/7] nir: add varying component packing helpers

On October 28, 2017 07:15:10 Bas Nieuwenhuizen wrote: On Mon, Oct 23, 2017 at 2:10 AM, Timothy Arceri wrote: --- src/compiler/nir/nir.h | 2 + src/compiler/nir/nir_linking_helpers.c | 235 + 2 files changed, 237 insertions(+) diff --git a/sr

[Mesa-dev] [PATCH v2] etnaviv: Allow clearing constant buffer using buffer==NULL user_buffer==NULL

Prevents an assertion when using GALLIUM_HUD with ioquake3, when cso_restore_constant_buffer_slot0 restores an empty constant buffer in slot 0. Signed-off-by: Wladimir J. van der Laan --- src/gallium/drivers/etnaviv/etnaviv_state.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Oops - ne

Re: [Mesa-dev] [PATCH 2/7] nir: add varying component packing helpers

On Mon, Oct 23, 2017 at 2:10 AM, Timothy Arceri wrote: > --- > src/compiler/nir/nir.h | 2 + > src/compiler/nir/nir_linking_helpers.c | 235 > + > 2 files changed, 237 insertions(+) > > diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h

Re: [Mesa-dev] [PATCH 7/7] radv: enable nir component packing

Reviewed-by: Bas Nieuwenhuizen On Mon, Oct 23, 2017 at 2:10 AM, Timothy Arceri wrote: > SaschaWillems Vulkan demo tessellation: > > ~4300fps -> ~4800fps > --- > src/amd/vulkan/radv_pipeline.c | 13 + > 1 file changed, 13 insertions(+) > > diff --git a/src/amd/vulkan/radv_pipeline.c

[Mesa-dev] [PATCH] etnaviv: Don't flush on transfer when UNSYNCHRONIZED

Structure code to only flush when we will potentially call cpu_prep. This prevents spurious flushes in applications that heavily rely on u_uploader. Signed-off-by: Wladimir J. van der Laan --- src/gallium/drivers/etnaviv/etnaviv_transfer.c | 24 1 file changed, 12 insert

[Mesa-dev] [PATCH] etnaviv: Allow clearing constant buffer using buffer==NULL user_buffer==NULL

Prevents an assertion when using GALLIUM_HUD with ioquake3, when cso_restore_constant_buffer_slot0 restores an empty constant buffer in slot 0. Signed-off-by: Wladimir J. van der Laan --- src/gallium/drivers/etnaviv/etnaviv_state.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --gi

[Mesa-dev] [Bug 102677] [OpenGL CTS] KHR-GL45.CommonBugs.CommonBug_PerVertexValidation fails

https://bugs.freedesktop.org/show_bug.cgi?id=102677 --- Comment #3 from Neil Roberts --- I’ve posted a v2 of Eduardo’s patches here: https://lists.freedesktop.org/archives/mesa-dev/2017-October/174550.html -- You are receiving this mail because: You are the assignee for the bug.___

[Mesa-dev] [Bug 103496] svga_screen.c:26:46: error: git_sha1.h: No such file or directory

https://bugs.freedesktop.org/show_bug.cgi?id=103496 Bug ID: 103496 Summary: svga_screen.c:26:46: error: git_sha1.h: No such file or directory Product: Mesa Version: git Hardware: x86-64 (AMD64) OS: Linux (Al