From: Michel Dänzer
Such buffers can only be useful by reading from them with the CPU, so we
need to make sure CPU reads are fast.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84178
Signed-off-by: Michel Dänzer
---
v2: Add Bugzilla tag
src/mesa/state_tracker/st_cb_bufferobjects.c |
From: Michel Dänzer
Such buffers can only be useful by reading from them with the CPU, so we
need to make sure CPU reads are fast.
Signed-off-by: Michel Dänzer
---
src/mesa/state_tracker/st_cb_bufferobjects.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/src/mesa/
On Monday, September 08, 2014 12:21:44 PM Matt Turner wrote:
> pow(x, y) is equivalent to exp(log(x) * y).
>
> instructions in affected programs: 578 -> 458 (-20.76%)
Impressive stats!
> ---
> src/glsl/opt_algebraic.cpp | 14 ++
> 1 file changed, 14 insertions(+)
>
> diff --git
From: Michel Dänzer
The draw module would still try to use gallivm, causing many piglit tests
to fail with an assertion failure. llvmpipe might have been similarly
affected.
Signed-off-by: Michel Dänzer
---
src/gallium/auxiliary/draw/draw_context.c | 2 --
src/gallium/auxiliary/draw/draw_ll
What happens is that a SPLIT operation is part of the spill node, and as
a pseudo op, the instruction gets erased after processing its first def.
However the later defs still need to refer to it, so instead delay
spilling until after that whole RA node is done processing.
Bugzilla: https://bugs.fr
On Wed, Sep 24, 2014 at 6:25 AM, Marc Dietrich wrote:
> Am Montag, 22. September 2014, 11:48:29 schrieb Matt Turner:
>> We need a configure check for support for __attribute__((target)). I'm
>> going to send a series that adds support for this (and does the check
>> for existing attribute uses, so
Hi Juliet,
sorry about the delay, thanks for the email. I don't personally work on mesa
so I'll wait if anyone on the list has a project to propose here.
On Sat, Sep 20, 2014 at 07:52:38PM +0100, Juliet Fru wrote:
> I am Juliet Fru, a second year student of Computer Engineering at the
> Universit
On Wed, Sep 24, 2014 at 12:28 PM, Kristian Høgsberg wrote:
> Here's a set of 16 patches to bring up mesa on Skylake (GEN 9). This is
> just initial enabling, there's more work to do. Most patches have been
> written/reviewed/signed-off by at least two developers and are ready to go.
> There are
On Wed, Sep 24, 2014 at 7:13 PM, Kristian Høgsberg wrote:
> On Wed, Sep 24, 2014 at 12:57 PM, Kenneth Graunke
> wrote:
>> On Wednesday, September 24, 2014 12:28:20 PM Kristian Høgsberg wrote:
>>
>>> On Skylake, the MOCS bits are an index into a table of 63 different,
>>
>>> configurable cache co
On Wed, Sep 24, 2014 at 3:57 PM, Dave Airlie wrote:
> On 25 September 2014 08:51, Ian Romanick wrote:
>> On 09/24/2014 12:52 PM, Eric Anholt wrote:
>>> Roland Scheidegger writes:
>>>
Oh yes and missing ALIGN + MAX2 too. I guess we could easily move these
to util code. That plus the thi
On Wed, Sep 24, 2014 at 12:57 PM, Kenneth Graunke wrote:
> On Wednesday, September 24, 2014 12:28:20 PM Kristian Høgsberg wrote:
>
>> On Skylake, the MOCS bits are an index into a table of 63 different,
>
>> configurable cache configurations. As for previous GENs, we only care
>> about
>
>> WB and
On Wed, Sep 24, 2014 at 3:33 PM, Anuj Phogat wrote:
> On Wed, Sep 24, 2014 at 12:28 PM, Kristian Høgsberg
> wrote:
>> From: Damien Lespiau
>>
>> This commands has seen the addition of 2 dwords that allow to specify
>> which channels of which attributes need to be forwarded to the fragment
>> sh
On 25 September 2014 08:51, Ian Romanick wrote:
> On 09/24/2014 12:52 PM, Eric Anholt wrote:
>> Roland Scheidegger writes:
>>
>>> Oh yes and missing ALIGN + MAX2 too. I guess we could easily move these
>>> to util code. That plus the things I already mentioned should be all
>>> needed I think. Bu
On 09/24/2014 12:52 PM, Eric Anholt wrote:
> Roland Scheidegger writes:
>
>> Oh yes and missing ALIGN + MAX2 too. I guess we could easily move these
>> to util code. That plus the things I already mentioned should be all
>> needed I think. But I strongly believe either this needs to be done or
>>
On Wed, Sep 24, 2014 at 12:28 PM, Kristian Høgsberg wrote:
> From: Damien Lespiau
>
> This commands has seen the addition of 2 dwords that allow to specify
> which channels of which attributes need to be forwarded to the fragment
> shader.
>
> v2: Rebase forward a year (done by Ken).
>
> Signed-o
Am 24.09.2014 23:23, schrieb Ilia Mirkin:
> On Wed, Sep 24, 2014 at 5:17 PM, Roland Scheidegger
> wrote:
>> I don't really qualified to review, IIRC I mentioned it was tricky to
>> see if it's right when you pushed it first, and this has not changed.
>> Some comment inline though...
>>
>>
>> Am 2
Am 24.09.2014 21:52, schrieb Eric Anholt:
> Roland Scheidegger writes:
>
>> Oh yes and missing ALIGN + MAX2 too. I guess we could easily move these
>> to util code. That plus the things I already mentioned should be all
>> needed I think. But I strongly believe either this needs to be done or
>>
On Wed, Sep 24, 2014 at 5:17 PM, Roland Scheidegger wrote:
> I don't really qualified to review, IIRC I mentioned it was tricky to
> see if it's right when you pushed it first, and this has not changed.
> Some comment inline though...
>
>
> Am 24.09.2014 20:30, schrieb Ilia Mirkin:
>> Marek/Roland
I don't really qualified to review, IIRC I mentioned it was tricky to
see if it's right when you pushed it first, and this has not changed.
Some comment inline though...
Am 24.09.2014 20:30, schrieb Ilia Mirkin:
> Marek/Roland -- do either of those comments count as a R-b? I'd like
> to push this
On Wed, Sep 24, 2014 at 1:39 PM, kalyan kondapally
wrote:
> This would ignore the case when record "A" is anonymous but record "B" is not.
Bah, I think you're right.
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On Wed, Sep 24, 2014 at 11:56 AM, Matt Turner wrote:
> On Mon, Sep 22, 2014 at 5:11 AM, Tapani Pälli wrote:
> > From: Kalyan Kondapally
> >
> > According to GLSL(4.2) and GLSL-ES (1.0, 3.0) spec, Structures must
> > have the same name to be considered same type. We currently ignore
> > the name
On Wed, Sep 24, 2014 at 12:28 PM, Kristian Høgsberg wrote:
> They are the same as for BDW, so just add a case for SKL to the init switch.
Confirmed. I should have added case 9 in my series, I suppose.
The BSpec isn't clear, but I think CHV and SKL have the same changes
for mixed-mode hf/f operat
On Wed, Sep 24, 2014 at 12:52 PM, Eric Anholt wrote:
> Roland Scheidegger writes:
>
>> Oh yes and missing ALIGN + MAX2 too. I guess we could easily move these
>> to util code. That plus the things I already mentioned should be all
>> needed I think. But I strongly believe either this needs to be
On Wednesday, September 24, 2014 12:28:21 PM Kristian Høgsberg wrote:
> As of BDW, this workaround is no longer necessary: "WM HW will internally
> manage
> the draining pipe and flushing of the caches when this commands is issued.
> The PIPE_CONTROL restrictions are removed."
>
> Signed-off-by: K
On Wednesday, September 24, 2014 12:28:13 PM Kristian Høgsberg wrote:
> From: Kenneth Graunke
>
> Otherwise they overlap and horrible things happen. All the new DWords
> are for fast color clear values, which we don't do yet.
This is no longer true. I see nothing prohibiting fast color clears f
On Wednesday, September 24, 2014 12:28:06 PM Kristian Høgsberg wrote:
> Signed-off-by: Kristian Høgsberg
> ---
> include/pci_ids/i965_pci_ids.h | 15 +++
> src/mesa/drivers/dri/i965/brw_device_info.c | 29
> +
> 2 files changed, 44 insertions(
On Wednesday, September 24, 2014 12:28:20 PM Kristian Høgsberg wrote:
> On Skylake, the MOCS bits are an index into a table of 63 different,
> configurable cache configurations. As for previous GENs, we only care about
> WB and WT, which are available in the documented default set. Define
> SKL_M
Roland Scheidegger writes:
> Oh yes and missing ALIGN + MAX2 too. I guess we could easily move these
> to util code. That plus the things I already mentioned should be all
> needed I think. But I strongly believe either this needs to be done or
> we should revert it.
What's the actual problem be
Here's a set of 16 patches to bring up mesa on Skylake (GEN 9). This is
just initial enabling, there's more work to do. Most patches have been
written/reviewed/signed-off by at least two developers and are ready to go.
There are a few new patches from me in the set that haven't been reviewed
yet:
From: Kenneth Graunke
We will need to allocate more DWords on Skylake.
Signed-off-by: Kenneth Graunke
Reviewed-by: Kristian Høgsberg
---
src/mesa/drivers/dri/i965/gen8_surface_state.c | 26 --
1 file changed, 16 insertions(+), 10 deletions(-)
diff --git a/src/mesa/dri
From: Kenneth Graunke
Skylake has some extra bits in PIPELINE_SELECT, none of which are
interesting for a 3D driver. In order to selectively change them, it
also introduces new "mask bits" in 15:8. We care about the "Pipeline
Selection" bits (1:0), so set the mask to 0x3.
Signed-off-by: Kennet
From: Kenneth Graunke
Skylake uploads the stencil reference values in DW3 of the
3DSTATE_WM_DEPTH_STENCIL packet, rather than in COLOR_CALC_STATE.
Signed-off-by: Kenneth Graunke
Reviewed-by: Kristian Høgsberg
---
src/mesa/drivers/dri/i965/brw_defines.h | 5 +
src/mesa/drivers/d
They are the same as for BDW, so just add a case for SKL to the init switch.
Signed-off-by: Kristian Høgsberg
---
src/mesa/drivers/dri/i965/brw_eu_compact.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_compact.c
b/src/mesa/drivers/dri/i965/brw_eu_compact.
From: Jordan Justen
Signed-off-by: Jordan Justen
Reviewed-by: Kristian Høgsberg
---
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 71
SKL updates the resolve rectangle scaling factors again.
Signed-off-by: Kristian Høgsberg
---
src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
b/src/mesa/drivers/dri/i965/br
From: Kenneth Graunke
On SKL, 3DSTATE_CONSTANT_* command is not committed until we give
the corresponding 3DSTATE_BINDING_TABLE_POINTERS_* command. If we
fail to do so, the constant buffers wont be read and push constants
will be wrong.
Signed-off-by: Kenneth Graunke
Reviewed-by: Kristian Høgs
From: Kenneth Graunke
Skylake has separate controls for enabling the Z Clip Test for the near
and far planes. For now, maintain the legacy behavior by setting both.
Signed-off-by: Kenneth Graunke
Reviewed-by: Kristian Høgsberg
---
src/mesa/drivers/dri/i965/brw_defines.h | 2 ++
src/mesa/d
From: Kenneth Graunke
Otherwise they overlap and horrible things happen. All the new DWords
are for fast color clear values, which we don't do yet.
Signed-off-by: Kenneth Graunke
Reviewed-by: Kristian Høgsberg
---
src/mesa/drivers/dri/i965/gen8_surface_state.c | 2 +-
1 file changed, 1 inser
Signed-off-by: Kristian Høgsberg
---
include/pci_ids/i965_pci_ids.h | 15 +++
src/mesa/drivers/dri/i965/brw_device_info.c | 29 +
2 files changed, 44 insertions(+)
diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
in
From: Kenneth Graunke
Skylake introduces a new base address for a feature we don't yet expose.
Setting these to 0 should be safe.
Signed-off-by: Kenneth Graunke
Reviewed-by: Kristian Høgsberg
---
src/mesa/drivers/dri/i965/gen8_misc_state.c | 13 +++--
1 file changed, 11 insertions(+),
On Skylake, the MOCS bits are an index into a table of 63 different,
configurable cache configurations. As for previous GENs, we only care about
WB and WT, which are available in the documented default set. Define
SKL_MOCS_WB and SKL_MOCS_WT to the indices for those configucations and use
those f
From: Jordan Justen
Signed-off-by: Jordan Justen
Reviewed-by: Kristian Høgsberg
---
src/mesa/drivers/dri/i965/intel_screen.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
b/src/mesa/drivers/dri/i965/intel_screen.c
index 41964ec..62e42aa 100644
--
From: Kenneth Graunke
Skylake's 3DSTATE_DS packet has a few more fields; we don't support
domain shaders yet though.
Signed-off-by: Kenneth Graunke
Reviewed-by: Kristian Høgsberg
---
src/mesa/drivers/dri/i965/gen8_disable.c | 15 +--
1 file changed, 5 insertions(+), 10 deletions(-
From: Damien Lespiau
This commands has seen the addition of 2 dwords that allow to specify
which channels of which attributes need to be forwarded to the fragment
shader.
v2: Rebase forward a year (done by Ken).
Signed-off-by: Damien Lespiau
Signed-off-by: Kenneth Graunke
Reviewed-by: Kristia
As of BDW, this workaround is no longer necessary: "WM HW will internally manage
the draining pipe and flushing of the caches when this commands is issued.
The PIPE_CONTROL restrictions are removed."
Signed-off-by: Kristian Høgsberg
---
src/mesa/drivers/dri/i965/gen8_depth_state.c | 2 --
src/m
Hi,
On Wednesday, September 24, 2014 12:42:24 Jose Fonseca wrote:
> We're not the only one with similar needs. Webkit has similar needs.
> Though they opted by using LLVMCreateSimpleMCJITMemoryManager
> https://trac.webkit.org/browser/trunk/Tools/ReducedFTL/ReducedFTL.c#L321
> and implemeti
On Mon, Sep 22, 2014 at 5:11 AM, Tapani Pälli wrote:
> From: Kalyan Kondapally
>
> According to GLSL(4.2) and GLSL-ES (1.0, 3.0) spec, Structures must
> have the same name to be considered same type. We currently ignore
> the name check while checking if two records are same. This patch
> fixes t
On Mon, Sep 22, 2014 at 5:11 AM, Tapani Pälli wrote:
> From: Kalyan Kondapally
>
> According to GLSL(4.2) and GLSL-ES (1.0, 3.0) spec, Structures must
> have the same name to be considered same type. We currently ignore
> the name check while checking if two records are same. This patch
> fixes t
Marek/Roland -- do either of those comments count as a R-b? I'd like
to push this out tonight, pending a full piglit run.
On Wed, Sep 24, 2014 at 1:35 PM, Roland Scheidegger wrote:
> Yes cubemaps should have array_size == 6 always in gallium. You just
> have to be careful whenever translating thi
On Wed, Sep 24, 2014 at 10:43 AM, Ian Romanick wrote:
> On 08/28/2014 08:10 PM, Matt Turner wrote:
>> ---
>> src/mesa/drivers/dri/i965/brw_eu_compact.c | 39
>> ++
>> 1 file changed, 24 insertions(+), 15 deletions(-)
>>
>> diff --git a/src/mesa/drivers/dri/i965/brw_eu
On Wed, Sep 24, 2014 at 10:41 AM, Ian Romanick wrote:
> There are a bunch of other places that do special things for
> BRW_OPCODE_NOP. Do any of those also need changes?
There's really not many. The main use of NOP is when we change the
opcode of an instruction we want to remove to NOP, and then
On Wed, Sep 24, 2014 at 10:36 AM, Ian Romanick wrote:
> On 08/28/2014 08:10 PM, Matt Turner wrote:
>> ---
>> src/mesa/drivers/dri/i965/brw_eu_compact.c | 17 +++--
>> 1 file changed, 7 insertions(+), 10 deletions(-)
>>
>> diff --git a/src/mesa/drivers/dri/i965/brw_eu_compact.c
>> b/s
Patches 1 through 4, 6, and 14 are
Reviewed-by: Ian Romanick
Assuming sufficient pigliting, patch 9 is
Acked-by: Ian Romanick
I sent a couple minor questions on a few others. The remaining will be
left to more capable hands.
On 08/28/2014 08:10 PM, Matt Turner wrote:
> This series adds inst
From: Christian König
This patch adds a skeleton VA-API state tracker,
which is filled with live in the subsequent patches.
v2: fixes in configure.ac and va state_tracker Makefile.am
Signed-off-by: Christian König
Signed-off-by: Leo Liu
---
configure.ac | 3
On 08/28/2014 08:10 PM, Matt Turner wrote:
> ---
> src/mesa/drivers/dri/i965/brw_eu_compact.c | 39
> ++
> 1 file changed, 24 insertions(+), 15 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_eu_compact.c
> b/src/mesa/drivers/dri/i965/brw_eu_compact.c
> i
There are a bunch of other places that do special things for
BRW_OPCODE_NOP. Do any of those also need changes?
On 08/28/2014 08:10 PM, Matt Turner wrote:
> ---
> src/mesa/drivers/dri/i965/brw_defines.h | 1 +
> src/mesa/drivers/dri/i965/brw_disasm.c | 5 +++--
> 2 files changed, 4 insertions(+
On 08/28/2014 08:10 PM, Matt Turner wrote:
> ---
> src/mesa/drivers/dri/i965/brw_eu_compact.c | 17 +++--
> 1 file changed, 7 insertions(+), 10 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_eu_compact.c
> b/src/mesa/drivers/dri/i965/brw_eu_compact.c
> index 5617947..dd3
Yes cubemaps should have array_size == 6 always in gallium. You just
have to be careful whenever translating things from mesa to gallium as
things like that won't be true in core mesa of course (similar to 1d
array textures having height and so on) due to OpenGL weirdness for
historical reasons.
R
Interesting, I didn't know about that. Nevermind. st/mesa indeed sets it to 6.
Marek
On Wed, Sep 24, 2014 at 6:26 PM, Ilia Mirkin wrote:
> On Wed, Sep 24, 2014 at 12:20 PM, Marek Olšák wrote:
>> Cubemaps have array_size == 1, but you can still set the target to 2D
>
> Are you *sure* about that?
On Wed, Aug 27, 2014 at 4:12 AM, Tapani Pälli wrote:
> Patch fixes the slot count used by vector types and adds 1 slot
> to be used by image and sampler types.
>
> Signed-off-by: Tapani Pälli
> https://bugs.freedesktop.org/show_bug.cgi?id=82921
Prefix with Bugzilla:
_
Reviewed-by: Matt Turner
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On Tue, Sep 23, 2014 at 12:50 PM, Jason Ekstrand wrote:
> On Thu, Aug 28, 2014 at 8:10 PM, Matt Turner wrote:
>>
>> The array was previously indexed in units of brw_compact_inst (8-bytes),
>> but before compaction all instructions are uncompacted, so every odd
>> element was unused.
>> ---
>> sr
Le mardi 23 septembre 2014, 16:23:03 Tom Stellard a écrit :
> LLVM commit r218316 removes the JITMemoryManager class, which is
> the parent for a seemingly important class in gallivm. In order to
> fix the build, I've wrapped most of lp_bld_misc.cpp in
> if HAVE_LLVM < 0x0306 and modifyed the
> lp
On Wed, Sep 24, 2014 at 12:20 PM, Marek Olšák wrote:
> Cubemaps have array_size == 1, but you can still set the target to 2D
Are you *sure* about that? Everything I'm seeing indicates that
cubemaps have array_size == 6. For example this code in nv50_tex.c:
depth = MAX2(mt->base.base.array_siz
Cubemaps have array_size == 1, but you can still set the target to 2D
and set first_layer <= last_layer <= 6 in the sample view. Instead of
checking array_size, maybe NumLayers should be used instead. Just
guessing.
Marek
On Wed, Sep 24, 2014 at 5:05 PM, Ilia Mirkin wrote:
> The disguise of cube
Nice catch.
Reviewed-by: Ian Romanick
On 09/24/2014 04:09 AM, Tapani Pälli wrote:
> ubo offsets are assigned by link_uniform_blocks since 514f8c7e
>
> Signed-off-by: Tapani Pälli
> ---
> src/glsl/link_uniforms.cpp | 34 --
> src/glsl/linker.h | 3 ---
Hi Emil,
>-Original Message-
>From: Emil Velikov [mailto:emil.l.veli...@gmail.com]
>Sent: Tuesday, September 23, 2014 3:49 PM
>To: Liu, Leo; mesa-dev@lists.freedesktop.org
>Cc: emil.l.veli...@gmail.com; Koenig, Christian
>Subject: Re: [Mesa-dev] [PATCH 2/6] st/va: skeleton VAAPI state tra
https://bugs.freedesktop.org/show_bug.cgi?id=84145
--- Comment #20 from smoki ---
Oh my it worked :), it is about s3tc i removed lib so picture is without s3tc
:D https://bugs.freedesktop.org/attachment.cgi?id=106762
So yeah, it is fixed for me too.
--
You are receiving this mail because:
https://bugs.freedesktop.org/show_bug.cgi?id=84145
--- Comment #19 from smoki ---
(In reply to comment #18)
> Weird.
>
> Mesa git master + *only* the last patch did fix it for me.
Weird or not, doublechecked and it does not work for me :). Previosly patched
with 45b104e0a228595142ed4bc62bbc894
The disguise of cubemap's layeredness is insufficient to trip up this
code :) They still get their NumLayers set, and the resources still
have an array size. Perhaps there's a scenario I'm not considering?
On Wed, Sep 24, 2014 at 5:23 AM, Marek Olšák wrote:
> Maybe something similar also needs to
Hi Jose,
On Wednesday, September 24, 2014 12:42:24 Jose Fonseca wrote:
> That said, the way we use these things are still a bit in flux. Mathias
> has some pending patches. BTW, Mathis, should I submit your patches
> for making llvmpipe thread safe? Also, what are your thoughts on this
> is
https://bugs.freedesktop.org/show_bug.cgi?id=84145
--- Comment #18 from Christoph Haag ---
Weird.
Mesa git master + *only* the last patch did fix it for me.
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Hi Juliet,
There's definitely work that can be done for Piglit. For example,
porting the old Glean tests to piglit's framework.
I suggest we move this conversation to the Piglit mailing list though.
The list is pig...@lists.freedesktop.org and you can subscribe at
http://lists.freedesktop.o
And use pass caller="" for _mesa_FramebufferTexture().
---
src/mesa/main/fbobject.c | 60 +++---
1 file changed, 30 insertions(+), 30 deletions(-)
diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c
index ae3a418..8283373 100644
--- a/src/mes
On Wed, Sep 24, 2014 at 8:31 AM, Timothy Arceri wrote:
> Hey guys,
>
> I don't think this is a Mesa issue but I didn't know where else to
> start. I tried using the #radeon channel but it wont let me post
> anything.
You have to be a registered user with nickserv on freenode to post in
#radeon, I
On Wed, Sep 24, 2014 at 9:31 AM, Timothy Arceri wrote:
> Hey guys,
>
> I don't think this is a Mesa issue but I didn't know where else to
> start. I tried using the #radeon channel but it wont let me post
> anything.
>
> I'm having some corruption and freezing issues with my 6670 that I would
> li
Hey guys,
I don't think this is a Mesa issue but I didn't know where else to
start. I tried using the #radeon channel but it wont let me post
anything.
I'm having some corruption and freezing issues with my 6670 that I would
like to help find the cause of. For more details and a screenshot see:
h
Hello,
Thanks for the reply. I'll download and build piglit, take a look at the
various tests written in it and either come up with a project to work on,
or wait for some ideas from mentors to take on as a project. I will like to
know whether any documentation work could be a viable project?
Than
Hi Matt,
Am Montag, 22. September 2014, 11:48:29 schrieb Matt Turner:
> On Fri, Sep 12, 2014 at 4:56 AM, Marc Dietrich wrote:
> > File specific optimization as used for src/mesa/main/streaming-load-memcpy.c
> > currently will cause problems with LTO in the future
> > (see: https://bugs.freedeskto
Tapani Pälli writes:
> Patch fixes the slot count used by vector types and adds 1 slot
> to be used by image and sampler types.
>
> Signed-off-by: Tapani Pälli
> https://bugs.freedesktop.org/show_bug.cgi?id=82921
> ---
> src/glsl/glsl_types.cpp | 18 +-
> src/glsl/glsl_types.h
On 23/09/14 21:23, Tom Stellard wrote:
LLVM commit r218316 removes the JITMemoryManager class, which is
the parent for a seemingly important class in gallivm. In order to
fix the build, I've wrapped most of lp_bld_misc.cpp in
if HAVE_LLVM < 0x0306 and modifyed the
lp_build_create_jit_compiler_f
On Wed, Sep 24, 2014 at 4:10 AM, Ian Romanick wrote:
> On 09/23/2014 03:39 PM, Erik Faye-Lund wrote:
>> Our current atan()-approximation is pretty inaccurate at 1.0, so
>> let's try to improve the situation by doing a direct approximation
>> without going through atan.
>>
>> This new implementatio
ubo offsets are assigned by link_uniform_blocks since 514f8c7e
Signed-off-by: Tapani Pälli
---
src/glsl/link_uniforms.cpp | 34 --
src/glsl/linker.h | 3 ---
2 files changed, 37 deletions(-)
diff --git a/src/glsl/link_uniforms.cpp b/src/glsl/link_unifor
On 22/09/14 00:44, Emil Velikov wrote:
> Avoid building the relatively large object every time and forcing
> on the non-vl targets. This gives us the following size improvement
>
>textdata bss dec hex filename
> 5898697 189212 1977864 8065773 7b12ed before/nouveau_dri.so
> 57
https://bugs.freedesktop.org/show_bug.cgi?id=84186
Michel Dänzer changed:
What|Removed |Added
Assignee|xorg-driver-...@lists.x.org |mesa-dev@lists.freedesktop.
Maybe something similar also needs to be done for cubemaps, because
they are just layered textures in disguise?
Marek
On Wed, Sep 24, 2014 at 7:01 AM, Ilia Mirkin wrote:
> For 3d textures, NumLayers is set to 1, which is not what we want. This
> fixes the newly added gl-layer-render-storage test
On Friday, September 19, 2014 05:47:58 PM Matt Turner wrote:
> On Thu, Aug 28, 2014 at 8:10 PM, Matt Turner wrote:
> > This series adds instruction compaction support for G45 and Gen5
> > and enables compaction of control flow instructions.
>
> Ken reviewed the first four patches I think. Can I ge
On Tuesday, September 23, 2014 01:25:55 PM Matt Turner wrote:
> On Tue, Sep 23, 2014 at 1:10 PM, Jason Ekstrand wrote:
> > On Thu, Aug 28, 2014 at 8:10 PM, Matt Turner wrote:
> >> +int jump = brw_inst_imm_d(brw, insn);
> >> +int jump_compacted = jump / sizeof(brw_compact_i
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