On Wednesday, September 24, 2014 12:28:21 PM Kristian Høgsberg wrote:
> As of BDW, this workaround is no longer necessary: "WM HW will internally
> manage
> the draining pipe and flushing of the caches when this commands is issued.
> The PIPE_CONTROL restrictions are removed."
>
> Signed-off-by: Kristian Høgsberg <k...@bitplanet.net>
> ---
> src/mesa/drivers/dri/i965/gen8_depth_state.c | 2 --
> src/mesa/drivers/dri/i965/intel_batchbuffer.c | 2 +-
> 2 files changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c
> b/src/mesa/drivers/dri/i965/gen8_depth_state.c
> index a0390f6..0d2877d 100644
> --- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
> +++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
> @@ -56,8 +56,6 @@ emit_depth_packets(struct brw_context *brw,
> return;
> }
>
> - intel_emit_depth_stall_flushes(brw);
> -
> /* _NEW_BUFFERS, _NEW_DEPTH, _NEW_STENCIL */
> BEGIN_BATCH(8);
> OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (8 - 2));
> diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> index cd45af6..0bc35bf 100644
> --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> @@ -535,7 +535,7 @@ brw_emit_pipe_control_write(struct brw_context *brw,
> uint32_t flags,
> void
> intel_emit_depth_stall_flushes(struct brw_context *brw)
> {
> - assert(brw->gen >= 6 && brw->gen <= 8);
> + assert(brw->gen >= 6 && brw->gen <= 7);
>
> brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL);
> brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_CACHE_FLUSH);
>Please make sure to do a full Piglit run (quick.py) on Broadwell with this change before pushing. (I wasn't sure if you ran it there, or just on Gen9.) It does look right, and I think I've tried that before too, but one can never be too careful about these things. Thanks Kristian! --Ken
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