Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.116 -> 1.117
---
Log message:
%fcc is not an alias for %fcc0
---
Diffs of the changes: (+4 -4)
SparcV8InstrInfo.td |8
1 files changed, 4 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/SparcV8
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.115 -> 1.116
---
Log message:
correct an opcode
---
Diffs of the changes: (+2 -2)
SparcV8InstrInfo.td |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/SparcV8/SparcV8InstrInfo
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.114 -> 1.115
---
Log message:
add conditional moves of float and double values on int/fp condition codes.
---
Diffs of the changes: (+27 -6)
SparcV8InstrInfo.td | 33 +++--
1 files ch
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.111 -> 1.112
---
Log message:
Add immediate forms of integer cmovs
---
Diffs of the changes: (+49 -6)
SparcV8InstrInfo.td | 55 ++--
1 files changed, 49 insertions
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.110 -> 1.111
---
Log message:
Shrinkify
---
Diffs of the changes: (+86 -143)
SparcV8InstrInfo.td | 229 +++-
1 files changed, 86 insertions(+), 143 deletions(-)
I
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.109 -> 1.110
---
Log message:
Add the full complement of conditional moves of integer registers.
---
Diffs of the changes: (+115 -7)
SparcV8InstrInfo.td | 122 +---
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.106 -> 1.107
---
Log message:
When in v9 mode, emit fabsd/fnegd/fmovd
---
Diffs of the changes: (+30 -8)
SparcV8InstrInfo.td | 38 ++
1 files changed, 30 insertions(+), 8 dele
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.99 -> 1.100
---
Log message:
Unbreak ret void :-/
---
Diffs of the changes: (+1 -0)
SparcV8InstrInfo.td |1 +
1 files changed, 1 insertion(+)
Index: llvm/lib/Target/SparcV8/SparcV8InstrInfo.td
diff -u llvm
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.98 -> 1.99
---
Log message:
Write this pattern in canonical form, allowing more patterns to match.
This implements Regression/CodeGen/SparcV8/xnor.ll
---
Diffs of the changes: (+1 -1)
SparcV8InstrInfo.td |2 +-
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.97 -> 1.98
SparcV8RegisterInfo.cpp updated: 1.32 -> 1.33
---
Log message:
New DAG node properties SNDPInFlag, SNDPOutFlag, and SNDPOptInFlag to replace
hasInFlag, hasOutFlag.
---
Diffs of the changes: (+7 -13)
Spa
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.96 -> 1.97
---
Log message:
Added field noResults to Instruction.
Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix t
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.95 -> 1.96
SparcV8RegisterInfo.cpp updated: 1.31 -> 1.32
---
Log message:
* Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead.
* Added a pseudo instruction (for each target) that represent "return void"
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.93 -> 1.94
---
Log message:
clean up .td file by using evan's new FLAG thing
---
Diffs of the changes: (+4 -4)
SparcV8InstrInfo.td |8
1 files changed, 4 insertions(+), 4 deletions(-)
Index: llvm/li
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.92 -> 1.93
---
Log message:
Correct bool truncstore operand order
---
Diffs of the changes: (+2 -2)
SparcV8InstrInfo.td |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/SparcV
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.91 -> 1.92
---
Log message:
add the other bool zextload as well
---
Diffs of the changes: (+1 -0)
SparcV8InstrInfo.td |1 +
1 files changed, 1 insertion(+)
Index: llvm/lib/Target/SparcV8/SparcV8InstrInfo.td
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.90 -> 1.91
---
Log message:
implement zextload bool
---
Diffs of the changes: (+3 -0)
SparcV8InstrInfo.td |3 +++
1 files changed, 3 insertions(+)
Index: llvm/lib/Target/SparcV8/SparcV8InstrInfo.td
diff -u l
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.89 -> 1.90
---
Log message:
Fix syntax for indirect calls. This fixes Olden/mst
---
Diffs of the changes: (+2 -2)
SparcV8InstrInfo.td |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/li
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.88 -> 1.89
---
Log message:
apparently rdy isn't actually a psuedo instruction. Use rd %y
---
Diffs of the changes: (+1 -1)
SparcV8InstrInfo.td |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: l
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.86 -> 1.87
---
Log message:
add bool truncstores
---
Diffs of the changes: (+6 -0)
SparcV8InstrInfo.td |6 ++
1 files changed, 6 insertions(+)
Index: llvm/lib/Target/SparcV8/SparcV8InstrInfo.td
diff -u l
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.84 -> 1.85
---
Log message:
add support for integer extloads
---
Diffs of the changes: (+9 -0)
SparcV8InstrInfo.td |9 +
1 files changed, 9 insertions(+)
Index: llvm/lib/Target/SparcV8/SparcV8InstrIn
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.78 -> 1.79
---
Log message:
remove some unused instructions
---
Diffs of the changes: (+0 -12)
SparcV8InstrInfo.td | 12
1 files changed, 12 deletions(-)
Index: llvm/lib/Target/SparcV8/SparcV8Inst
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.74 -> 1.75
---
Log message:
Claiming that branch targets are registers is not very wholesome. Change them
to be basic blocks. Also, add uncond branches.
---
Diffs of the changes: (+56 -51)
SparcV8InstrInfo.td |
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.73 -> 1.74
---
Log message:
Add unordered comparisons
---
Diffs of the changes: (+8 -13)
SparcV8InstrInfo.td | 21 -
1 files changed, 8 insertions(+), 13 deletions(-)
Index: llvm/lib/Target
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.72 -> 1.73
---
Log message:
Add patterns to the rest of the int condbranches and some of the fp branches
---
Diffs of the changes: (+46 -23)
SparcV8InstrInfo.td | 69 ++---
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.70 -> 1.71
SparcV8ISelSimple.cpp updated: 1.94 -> 1.95
---
Log message:
Eliminate CMPri, which is a synonym for SUBCCri
---
Diffs of the changes: (+3 -8)
SparcV8ISelSimple.cpp |2 +-
SparcV8InstrInfo.td |
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.68 -> 1.69
---
Log message:
Add patterns for fround/fextend and the funny fsmuld instruction
---
Diffs of the changes: (+8 -4)
SparcV8InstrInfo.td | 12
1 files changed, 8 insertions(+), 4 deletions
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.67 -> 1.68
---
Log message:
Add FP +,-,*,/
---
Diffs of the changes: (+16 -8)
SparcV8InstrInfo.td | 24
1 files changed, 16 insertions(+), 8 deletions(-)
Index: llvm/lib/Target/SparcV8
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.63 -> 1.64
---
Log message:
remove some unused instructions
---
Diffs of the changes: (+6 -81)
SparcV8InstrInfo.td | 87 +++-
1 files changed, 6 insertions(+), 81
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.62 -> 1.63
---
Log message:
add andn/orn/xorn patterns. This allows us to compile this:
long %test(ubyte, short, long %X, long %Y) {
%A = xor long %X, -1
%B = and long %Y, %A
ret long %B
}
to this:
test:
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.61 -> 1.62
---
Log message:
add patterns for FP stores
---
Diffs of the changes: (+12 -20)
SparcV8InstrInfo.td | 32
1 files changed, 12 insertions(+), 20 deletions(-)
Index: l
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.60 -> 1.61
---
Log message:
Add [reg+reg] integer stores
---
Diffs of the changes: (+15 -0)
SparcV8InstrInfo.td | 15 +++
1 files changed, 15 insertions(+)
Index: llvm/lib/Target/SparcV8/SparcV8Ins
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.59 -> 1.60
---
Log message:
Add store patterns
---
Diffs of the changes: (+6 -3)
SparcV8InstrInfo.td |9 ++---
1 files changed, 6 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/SparcV8/SparcV8Instr
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.58 -> 1.59
---
Log message:
add fp load patterns, switch rest of loads and stores to use addrmodes
---
Diffs of the changes: (+28 -30)
SparcV8InstrInfo.td | 58 +--
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.57 -> 1.58
---
Log message:
Add integer load[r+r] forms.
---
Diffs of the changes: (+23 -0)
SparcV8InstrInfo.td | 23 +++
1 files changed, 23 insertions(+)
Index: llvm/lib/Target/SparcV8/Sp
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.56 -> 1.57
---
Log message:
Add patterns for the rest of the loads. Add 'ri' suffixes to the load and
store insts
---
Diffs of the changes: (+35 -31)
SparcV8InstrInfo.td | 66 +++---
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.54 -> 1.55
---
Log message:
Use a combination of sethi and or to build arbitrary immediates.
---
Diffs of the changes: (+7 -0)
SparcV8InstrInfo.td |7 +++
1 files changed, 7 insertions(+)
Index: llvm/lib
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.52 -> 1.53
---
Log message:
Add shift and small immediate support
---
Diffs of the changes: (+20 -6)
SparcV8InstrInfo.td | 26 --
1 files changed, 20 insertions(+), 6 deletions(-)
Index
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.51 -> 1.52
---
Log message:
Add some basic reg-reg instructions
---
Diffs of the changes: (+10 -5)
SparcV8InstrInfo.td | 15 ++-
1 files changed, 10 insertions(+), 5 deletions(-)
Index: llvm/lib/Ta
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.49 -> 1.50
---
Log message:
Add some simple integer patterns. This allows us to compile this:
int %test(int %A) {
%B = add int %A, 1
%C = xor int %B, 123
ret int %C
}
into this:
test:
save -96, %sp, %
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.48 -> 1.49
---
Log message:
Add a pattern for 'ret'. This now compiles:
void %test() { ret void }
:)
---
Diffs of the changes: (+1 -1)
SparcV8InstrInfo.td |2 +-
1 files changed, 1 insertion(+), 1 deletion
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.39 -> 1.40
---
Log message:
add some simple operand info
---
Diffs of the changes: (+8 -7)
SparcV8InstrInfo.td | 15 ---
1 files changed, 8 insertions(+), 7 deletions(-)
Index: llvm/lib/Target/Spar
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