Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.106 -> 1.107
---
Log message:
When in v9 mode, emit fabsd/fnegd/fmovd
---
Diffs of the changes: (+30 -8)
SparcV8InstrInfo.td | 38 ++++++++++++++++++++++++++++++--------
1 files changed, 30 insertions(+), 8 deletions(-)
Index: llvm/lib/Target/SparcV8/SparcV8InstrInfo.td
diff -u llvm/lib/Target/SparcV8/SparcV8InstrInfo.td:1.106
llvm/lib/Target/SparcV8/SparcV8InstrInfo.td:1.107
--- llvm/lib/Target/SparcV8/SparcV8InstrInfo.td:1.106 Sun Jan 29 23:35:57 2006
+++ llvm/lib/Target/SparcV8/SparcV8InstrInfo.td Sun Jan 29 23:48:37 2006
@@ -25,6 +25,11 @@
// instructions. Note that the machine may be running in 32-bit mode.
def HasV9 : Predicate<"Subtarget.isV9()">;
+// HasNoV9 - This predicate is true when the target doesn't have V9
+// instructions. Use of this is just a hack for the isel not having proper
+// costs for V8 instructions that are more expensive than their V9 ones.
+def HasNoV9 : Predicate<"!Subtarget.isV9()">;
+
// HasVIS - This is true when the target processor has VIS extensions.
def HasVIS : Predicate<"Subtarget.isVIS()">;
@@ -140,14 +145,16 @@
// FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the
// fpmover pass.
-def FpMOVD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
- "!FpMOVD $src, $dst", []>; // pseudo 64-bit double move
-def FpNEGD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
- "!FpNEGD $src, $dst",
- [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>;
-def FpABSD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
- "!FpABSD $src, $dst",
- [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>;
+let Predicates = [HasNoV9] in { // Only emit these in V8 mode.
+ def FpMOVD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
+ "!FpMOVD $src, $dst", []>;
+ def FpNEGD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
+ "!FpNEGD $src, $dst",
+ [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>;
+ def FpABSD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
+ "!FpABSD $src, $dst",
+ [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>;
+}
// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by
the
// scheduler into a branch sequence. This has to handle all permutations of
@@ -742,6 +749,21 @@
(V8selecticc IntRegs:$F, IntRegs:$T, 17, ICC))]>;
}
+// Floating-Point Move Instructions, p. 164 of the V9 manual.
+let Predicates = [HasV9] in {
+ def FMOVD : F3_3<2, 0b110100, 0b000000010,
+ (ops DFPRegs:$dst, DFPRegs:$src),
+ "fmovd $src, $dst", []>;
+ def FNEGD : F3_3<2, 0b110100, 0b000000110,
+ (ops DFPRegs:$dst, DFPRegs:$src),
+ "fnegd $src, $dst",
+ [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>;
+ def FABSD : F3_3<2, 0b110100, 0b000001010,
+ (ops DFPRegs:$dst, DFPRegs:$src),
+ "fabsd $src, $dst",
+ [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>;
+}
+
//===----------------------------------------------------------------------===//
// Non-Instruction Patterns
//===----------------------------------------------------------------------===//
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