Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.96 -> 1.97
---
Log message:
Added field noResults to Instruction.
Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.
---
Diffs of the changes: (+4 -2)
SparcV8InstrInfo.td | 6 ++++--
1 files changed, 4 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/SparcV8/SparcV8InstrInfo.td
diff -u llvm/lib/Target/SparcV8/SparcV8InstrInfo.td:1.96
llvm/lib/Target/SparcV8/SparcV8InstrInfo.td:1.97
--- llvm/lib/Target/SparcV8/SparcV8InstrInfo.td:1.96 Fri Dec 23 16:14:32 2005
+++ llvm/lib/Target/SparcV8/SparcV8InstrInfo.td Mon Dec 26 03:11:45 2005
@@ -171,7 +171,7 @@
// Section A.3 - Synthetic Instructions, p. 85
// special cases of JMPL:
-let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
+let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, noResults = 1 in {
let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
// FIXME: temporary workaround for return without an incoming flag.
def RETVOID: F3_2<2, 0b111000, (ops), "retl", [(ret)]>;
@@ -466,6 +466,7 @@
let isBranch = 1;
let isTerminator = 1;
let hasDelaySlot = 1;
+ let noResults = 1;
}
let isBarrier = 1 in
@@ -511,6 +512,7 @@
let isBranch = 1;
let isTerminator = 1;
let hasDelaySlot = 1;
+ let noResults = 1;
}
def FBU : FPBranchV8<0b0111, (ops brtarget:$dst),
@@ -561,7 +563,7 @@
// Section B.24 - Call and Link Instruction, p. 125
// This is the only Format 1 instruction
let Uses = [O0, O1, O2, O3, O4, O5],
- hasDelaySlot = 1, isCall = 1, hasInFlag = 1, hasOutFlag = 1,
+ hasDelaySlot = 1, isCall = 1, hasInFlag = 1, hasOutFlag = 1, noResults = 1,
Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in {
def CALL : InstV8<(ops calltarget:$dst),
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