Greetings.
We're using a board derived from the MPC8315E. Fairly regularly, the
SATA connection will freeze up while we are writing to flash memory:
[ 839.806884] ata2.00: exception Emask 0x10 SAct 0x0 SErr 0x0 action 0x6
frozen
[ 839.814201] ata2.00: failed command: WRITE DMA
[ 839.8
On Wed, May 15, 2013 at 03:58:57PM +1000, Benjamin Herrenschmidt wrote:
>On Wed, 2013-05-15 at 13:30 +0800, Gavin Shan wrote:
>> >There is an error injection framework we can use nowadays, or maybe you can
>> >put this in tools/powerpc ?
>> >
>>
>> Ben, we don't have error injection framework yet.
The Kconfig entry that allows to "Distribute interrupts on all CPUs by
default" has a (negative) dependency on MV64360. But that Kconfig symbol
was removed in v2.6.27, which means that this dependency has evaluated
to true ever since. It can be removed too.
Signed-off-by: Paul Bolle
---
Tested by
On Wed, 2013-05-15 at 16:47 +0800, Gavin Shan wrote:
>
> Ok. Ben. Could you please point me the source code of the error
> injection framework? :-)
> I think you're not talking about userland utility "errinject".
It's minimal, it's just the stuff in lib/fault-inject which provides
a framework for
On 05/06/2013 11:32 AM, Alex Deucher wrote:
On Fri, May 3, 2013 at 7:01 PM, Benjamin Herrenschmidt
wrote:
On Fri, 2013-05-03 at 19:43 -0300, Kleber Sacilotto de Souza wrote:
This patch series does:
1. max_bus_speed is used to set the device to gen2 speeds
2. on power there's no longer a
On Wed, May 15, 2013 at 8:35 AM, Kleber Sacilotto de Souza
wrote:
> On 05/06/2013 11:32 AM, Alex Deucher wrote:
>>
>> On Fri, May 3, 2013 at 7:01 PM, Benjamin Herrenschmidt
>> wrote:
>>>
>>> On Fri, 2013-05-03 at 19:43 -0300, Kleber Sacilotto de Souza wrote:
>>>
This patch series does:
On 05/15/2013 09:58 AM, Alex Deucher wrote:
On Wed, May 15, 2013 at 8:35 AM, Kleber Sacilotto de Souza
wrote:
On 05/06/2013 11:32 AM, Alex Deucher wrote:
On Fri, May 3, 2013 at 7:01 PM, Benjamin Herrenschmidt
wrote:
On Fri, 2013-05-03 at 19:43 -0300, Kleber Sacilotto de Souza wrote:
This
On Wed 15 May 2013 02:52:51 AM CST, Yinghai Lu wrote:
On Tue, May 14, 2013 at 9:57 AM, Liu Jiang wrote:
On Tue 14 May 2013 11:10:33 PM CST, Yinghai Lu wrote:
On Tue, May 14, 2013 at 7:59 AM, Liu Jiang wrote:
On 05/14/2013 04:26 PM, Gu Zheng wrote:
I suggest to use pci_release_dev() i
On Wed, May 15, 2013 at 7:39 AM, Liu Jiang wrote:
> On Wed 15 May 2013 02:52:51 AM CST, Yinghai Lu wrote:
>>
>> On Tue, May 14, 2013 at 9:57 AM, Liu Jiang wrote:
>>>
>>> On Tue 14 May 2013 11:10:33 PM CST, Yinghai Lu wrote:
On Tue, May 14, 2013 at 7:59 AM, Liu Jiang wrote:
>
>
On Wed 15 May 2013 10:43:02 PM CST, Yinghai Lu wrote:
On Wed, May 15, 2013 at 7:39 AM, Liu Jiang wrote:
On Wed 15 May 2013 02:52:51 AM CST, Yinghai Lu wrote:
On Tue, May 14, 2013 at 9:57 AM, Liu Jiang wrote:
On Tue 14 May 2013 11:10:33 PM CST, Yinghai Lu wrote:
On Tue, May 14, 2013 at 7
On Wed, May 15, 2013 at 7:46 AM, Liu Jiang wrote:
> On Wed 15 May 2013 10:43:02 PM CST, Yinghai Lu wrote:
>>
>
>> that is another bug, let of guy handle it.
>>
>> Yinghai
>
> Hi Yinghai,
> I don't know any OF exports, could you please help to CC
> some OF experts?
powerpc and sparc are usin
On 05/15/2013 07:30 AM, Benjamin Herrenschmidt wrote:
On Wed, 2013-05-15 at 00:51 +0800, Jiang Liu wrote:
Enhance PPC architecture specific code to use hotplug-safe iterators
to walk PCI buses.
I was about to ack it but then I saw:
diff --git a/arch/powerpc/kernel/pci_64.c b/arch/powerpc/kern
Enhance PPC architecture specific code to use hotplug-safe iterators
to walk PCI buses.
Signed-off-by: Jiang Liu
Cc: Benjamin Herrenschmidt
Cc: Paul Mackerras
Cc: Gavin Shan
Cc: Greg Kroah-Hartman
Cc: Grant Likely
Cc: Bill Pemberton
Cc: Yinghai Lu
Cc: linuxppc-dev@lists.ozlabs.org
Cc: linu
On Wed 15 May 2013 08:32:34 AM CST, Benjamin Herrenschmidt wrote:
On Wed, 2013-05-08 at 23:51 +0800, Jiang Liu wrote:
Prepare for removing num_physpages and simplify mem_init().
No objection, I haven't had a chance to actually build/boot test though.
BTW. A recommended way of doing so which i
On Wed, 2013-05-15 at 22:46 +0800, Liu Jiang wrote:
>I don't know any OF exports, could you please help to CC
> some OF experts?
I wrote that code I think. Sorry, I've missed the beginning of the
thread, what is the problem ?
Cheers,
Ben.
___
On 05/13/2013 09:03:17 PM, Kevin Hao wrote:
On Mon, May 13, 2013 at 10:47:17AM -0500, Scott Wood wrote:
> On 05/11/2013 06:26:21 PM, Kevin Hao wrote:
> >In the external proxy facility mode, the interrupt is automatically
> >acknowledged with the same effect as reading the IACK register. So
> >thi
On Wed, 2013-05-15 at 07:58 -0700, Yinghai Lu wrote:
> Ben,
>
> in drivers/pci/probe.c::pci_scan_device() there is
>
> pci_set_of_node(dev);
>
> if (pci_setup_device(dev)) {
> kfree(dev);
> return NULL;
> }
>
> so if pci_setup_device fail
On Wed, May 15, 2013 at 2:32 PM, Benjamin Herrenschmidt
wrote:
> On Wed, 2013-05-15 at 07:58 -0700, Yinghai Lu wrote:
>
>> Ben,
>>
>> in drivers/pci/probe.c::pci_scan_device() there is
>>
>> pci_set_of_node(dev);
>>
>> if (pci_setup_device(dev)) {
>> kfree(dev);
>>
On Thu 16 May 2013 05:29:31 AM CST, Benjamin Herrenschmidt wrote:
On Wed, 2013-05-15 at 22:46 +0800, Liu Jiang wrote:
I don't know any OF exports, could you please help to CC
some OF experts?
I wrote that code I think. Sorry, I've missed the beginning of the
thread, what is the problem
On Wed, May 15, 2013 at 07:48:44PM +1000, Benjamin Herrenschmidt wrote:
>On Wed, 2013-05-15 at 16:47 +0800, Gavin Shan wrote:
>>
>> Ok. Ben. Could you please point me the source code of the error
>> injection framework? :-)
>> I think you're not talking about userland utility "errinject".
>
>It's
Hi folks !
So I was trying to use my 5020ds to test some stuff today. Since I
hadn't used it in a while, I decided to "upgrade" it to the latest NOR
etc...
Interestingly I discovered that the SATA (which was supposedly dead on
the rev1 chip) was actually working with the SDK kernel, while it's
st
From: Bharat Bhushan
Bharat Bhushan (2):
powerpc: debug control and status registers are 32bit
=> This patch makes debug control and status registers as 32bit as they are.
This does not fix anything
powerpc: restore dbcr0 on user space exit
=> This patch fixes the ptrace reliability issue
Signed-off-by: Bharat Bhushan
---
arch/powerpc/include/asm/processor.h |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/processor.h
b/arch/powerpc/include/asm/processor.h
index d7e67ca..5213577 100644
--- a/arch/powerpc/include/asm/processo
On BookE (Branch taken + Single Step) is as same as Branch Taken
on BookS and in Linux we simulate BookS behavior for BookE as well.
When doing so, in Branch taken handling we want to set DBCR0_IC but
we update the current->thread->dbcr0 and not DBCR0.
Now on 64bit the current->thread.dbcr0 (and o
From: Bharat Bhushan
v1->v2
- Subject line was missing 0/2, 1/2, 2/2
Bharat Bhushan (2):
powerpc: debug control and status registers are 32bit
=> This patch makes debug control and status registers as 32bit as they are.
This does not fix anything
powerpc: restore dbcr0 on user space exi
Signed-off-by: Bharat Bhushan
---
v1->v2
- Subject line was not having 1/2
arch/powerpc/include/asm/processor.h |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/processor.h
b/arch/powerpc/include/asm/processor.h
index d7e67ca..5213577 100
On BookE (Branch taken + Single Step) is as same as Branch Taken
on BookS and in Linux we simulate BookS behavior for BookE as well.
When doing so, in Branch taken handling we want to set DBCR0_IC but
we update the current->thread->dbcr0 and not DBCR0.
Now on 64bit the current->thread.dbcr0 (and o
On Thu, 2013-05-16 at 14:47 +1000, Benjamin Herrenschmidt wrote:
> Hi folks !
>
> So I was trying to use my 5020ds to test some stuff today. Since I
> hadn't used it in a while, I decided to "upgrade" it to the latest NOR
> etc...
On another note, I can't seem to get any PCIe card recognized in a
On 05/16/2013 01:45 PM, Benjamin Herrenschmidt wrote:
On Thu, 2013-05-16 at 14:47 +1000, Benjamin Herrenschmidt wrote:
Hi folks !
So I was trying to use my 5020ds to test some stuff today. Since I
hadn't used it in a while, I decided to "upgrade" it to the latest NOR
etc...
On another note, I
For PCIe issue, I might be related to your RCW (Reset Configuration Word).
Can you help to provide the u-boot log?
Roy
> -Original Message-
> From: Linuxppc-dev [mailto:linuxppc-dev-bounces+tie-
> fei.zang=freescale@lists.ozlabs.org] On Behalf Of Benjamin
> Herrenschmidt
> Sent: Thursd
> -Original Message-
> From: Linuxppc-dev [mailto:linuxppc-dev-
> bounces+bharat.bhushan=freescale@lists.ozlabs.org] On Behalf Of Benjamin
> Herrenschmidt
> Sent: Thursday, May 16, 2013 11:16 AM
> To: Liu Qiang-B32616
> Cc: linuxppc-dev@lists.ozlabs.org; Fleming Andy-AFLEMING; Xie Sha
> -Original Message-
> From: Linuxppc-dev [mailto:linuxppc-dev-bounces+tie-
> fei.zang=freescale@lists.ozlabs.org] On Behalf Of Bhushan Bharat-
> R65777
> Sent: Thursday, May 16, 2013 2:02 PM
> To: Benjamin Herrenschmidt; Liu Qiang-B32616
> Cc: Fleming Andy-AFLEMING; linuxppc-dev@list
On Thu, 2013-05-16 at 13:55 +0800, tiejun.chen wrote:
> This should depend on the RCW.
>
> As I recall, slot 7 or slot 4 can be configured to support PCIe for
> P5020DS. And
> you can know this information according to RCW's README.
Somebody can hand hold me on irc ?
Cheers,
Ben.
On Thu, 2013-05-16 at 06:05 +, Zang Roy-R61911 wrote:
> I do not suggest changing the RCW. If the RCW is broken on Ben's side,
> it is not easy to recover for him.
> Let's check the U-boot output first.
U-Boot 2013.01-9-g7bcd7f4 (Mar 14 2013 - 14:23:16)
CPU0: P5020E, Version: 1.0, (0x822
Do you try slot7?
PCIe1 connects to slot7 directly.
Roy
> -Original Message-
> From: Benjamin Herrenschmidt [mailto:b...@kernel.crashing.org]
> Sent: Thursday, May 16, 2013 2:09 PM
> To: Zang Roy-R61911
> Cc: Bhushan Bharat-R65777; Liu Qiang-B32616; Fleming Andy-AFLEMING;
> linuxppc-dev@li
On 05/16/2013 02:09 PM, Benjamin Herrenschmidt wrote:
On Thu, 2013-05-16 at 06:05 +, Zang Roy-R61911 wrote:
I do not suggest changing the RCW. If the RCW is broken on Ben's side,
it is not easy to recover for him.
Let's check the U-boot output first.
U-Boot 2013.01-9-g7bcd7f4 (Mar 14 2
This is a revert and then some of commit 860aad7 "Add regs_no_sipr()".
This workaround was only needed on early chip versions.
As before NO_SIPR becomes a static flag of the PMU struct.
Signed-off-by: Michael Ellerman
---
arch/powerpc/perf/core-book3s.c | 30 ++
1
Commit 8f61aa3 "Add support for SIER" missed updates to siar_valid()
and perf_get_data_addr().
In both cases we need to check the SIER instead of mmcra.
Signed-off-by: Michael Ellerman
---
arch/powerpc/perf/core-book3s.c | 37 +
1 file changed, 25 insertion
> -Original Message-
> From: tiejun.chen [mailto:tiejun.c...@windriver.com]
> Sent: Thursday, May 16, 2013 2:18 PM
> To: Benjamin Herrenschmidt
> Cc: Zang Roy-R61911; Liu Qiang-B32616; Fleming Andy-AFLEMING; linuxppc-
> d...@lists.ozlabs.org; Xie Shaohui-B21989; Bhushan Bharat-R65777
> Su
On Thu, 2013-05-16 at 14:17 +0800, tiejun.chen wrote:
> I think you can use Bharat's RCW, which seems RR_HXAPNSP_0x36, then
> please take
> a look at this:
Ok, how do I update my RCW to bse Bharat's ?
Any DIP switch setting I need to be aware of ?
Thanks !
Cheers,
Ben.
__
On Thu, 2013-05-16 at 06:17 +, Zang Roy-R61911 wrote:
> Do you try slot7?
> PCIe1 connects to slot7 directly.
I tried all slots. None of them sees any card. The card also doesn't
seem to be powered up (none of the LEDs blink, it's an e1000 since I
don't have networking with upstream).
I also
Hi, Ben,
Since the p5020ds you tested is a rev1 chip, I think the most possibility that
SATA not work
is due to a SATA erratum, which is fixed in rev1.1, we have a policy that
patches for errata that
are present only on early silicon revisions, typically only rev1 silicon will
not send upstrea
On 05/16/2013 02:20 PM, Zang Roy-R61911 wrote:
-Original Message-
From: tiejun.chen [mailto:tiejun.c...@windriver.com]
Sent: Thursday, May 16, 2013 2:18 PM
To: Benjamin Herrenschmidt
Cc: Zang Roy-R61911; Liu Qiang-B32616; Fleming Andy-AFLEMING; linuxppc-
d...@lists.ozlabs.org; Xie Shao
On Thu, 2013-05-16 at 06:20 +, Zang Roy-R61911 wrote:
> Why?
> Ben's on board RCW protocol is 0x36, which should work for PCIe1 (slot 7) and
> PCIe3 (slot4).
> Roy
I've put a card in slot 7 and a card in slot 4 and I still get:
PCIe1: Root Complex, no link, regs @ 0xfe20
PCIe1: Bus 00 -
All these boards use the same configuration file p1_p2_rdb_pc.h in
u-boot. So they have the same pci bus address set by the u-boot.
But in some of these boards the bus address set in dtb don't match
the one used by u-boot. And this will trigger a kernel bug in 32bit
kernel and cause the pci device
On Thu, 2013-05-16 at 06:24 +, Xie Shaohui-B21989 wrote:
> Hi, Ben,
>
> Since the p5020ds you tested is a rev1 chip, I think the most possibility
> that SATA not work
> is due to a SATA erratum, which is fixed in rev1.1, we have a policy that
> patches for errata that
> are present only on
Try:
>From bank 0
tftp 0x100 rcw_2sgmii_1500mhz.bin
protect off 0xec00 +$filesize; erase 0xec00 +$filesize; cp.b 0x100
0xec00 $filesize
Thanks
-Bharat
> -Original Message-
> From: Benjamin Herrenschmidt [mailto:b...@kernel.crashing.org]
> Sent: Thursd
On Thu, 2013-05-16 at 06:33 +, Bhushan Bharat-R65777 wrote:
> From bank 0
>
>
> tftp 0x100 rcw_2sgmii_1500mhz.bin
> protect off 0xec00 +$filesize; erase 0xec00 +$filesize; cp.b
> 0x100 0xec00 $filesize
Before I do something irreparable, what do you specifical
> -Original Message-
> From: Bhushan Bharat-R65777
> Sent: Thursday, May 16, 2013 2:33 PM
> To: Benjamin Herrenschmidt; Zang Roy-R61911
> Cc: Liu Qiang-B32616; Fleming Andy-AFLEMING; linuxppc-
> d...@lists.ozlabs.org; Xie Shaohui-B21989
> Subject: RE: SATA FSL and upstreaming
>
> Try:
>
On 05/16/2013 02:21 PM, Benjamin Herrenschmidt wrote:
On Thu, 2013-05-16 at 14:17 +0800, tiejun.chen wrote:
I think you can use Bharat's RCW, which seems RR_HXAPNSP_0x36, then
please take
a look at this:
Ok, how do I update my RCW to bse Bharat's ?
Firstly please check which flash bank is u
On Thu, 2013-05-16 at 06:33 +, Bhushan Bharat-R65777 wrote:
> protect off 0xec00 +$filesize; erase 0xec00 +$filesize; cp.b
> 0x100 0xec00 $filesize
BTW, is it normal that the network in uboot is *extremely* unreliable ?
It takes dozens of tries if not more for it to "kick in",
> -Original Message-
> From: tiejun.chen [mailto:tiejun.c...@windriver.com]
> Sent: Thursday, May 16, 2013 2:36 PM
> To: Benjamin Herrenschmidt
> Cc: Zang Roy-R61911; Liu Qiang-B32616; Fleming Andy-AFLEMING; linuxppc-
> d...@lists.ozlabs.org; Xie Shaohui-B21989; Bhushan Bharat-R65777
> Su
On Thu, 2013-05-16 at 14:35 +0800, tiejun.chen wrote:
> On 05/16/2013 02:21 PM, Benjamin Herrenschmidt wrote:
> > On Thu, 2013-05-16 at 14:17 +0800, tiejun.chen wrote:
> >> I think you can use Bharat's RCW, which seems RR_HXAPNSP_0x36, then
> >> please take
> >> a look at this:
> >
> > Ok, how do I
On 05/16/2013 02:37 PM, Benjamin Herrenschmidt wrote:
On Thu, 2013-05-16 at 06:33 +, Bhushan Bharat-R65777 wrote:
protect off 0xec00 +$filesize; erase 0xec00 +$filesize; cp.b
0x100 0xec00 $filesize
BTW, is it normal that the network in uboot is *extremely* unreliable ?
We
On 05/16/2013 02:40 PM, Benjamin Herrenschmidt wrote:
On Thu, 2013-05-16 at 14:35 +0800, tiejun.chen wrote:
On 05/16/2013 02:21 PM, Benjamin Herrenschmidt wrote:
On Thu, 2013-05-16 at 14:17 +0800, tiejun.chen wrote:
I think you can use Bharat's RCW, which seems RR_HXAPNSP_0x36, then
please tak
> -Original Message-
> From: Bhushan Bharat-R65777
> Sent: Thursday, May 16, 2013 2:33 PM
> To: Benjamin Herrenschmidt; Zang Roy-R61911
> Cc: Liu Qiang-B32616; Fleming Andy-AFLEMING; linuxppc-
> d...@lists.ozlabs.org; Xie Shaohui-B21989
> Subject: RE: SATA FSL and upstreaming
>
> Try:
>
> -Original Message-
> From: tiejun.chen [mailto:tiejun.c...@windriver.com]
> Sent: Thursday, May 16, 2013 12:13 PM
> To: Benjamin Herrenschmidt
> Cc: Zang Roy-R61911; Liu Qiang-B32616; Fleming Andy-AFLEMING; linuxppc-
> d...@lists.ozlabs.org; Xie Shaohui-B21989; Bhushan Bharat-R65777
> S
> -Original Message-
> From: Bhushan Bharat-R65777
> Sent: Thursday, May 16, 2013 2:48 PM
> To: tiejun.chen; Benjamin Herrenschmidt
> Cc: Zang Roy-R61911; Liu Qiang-B32616; Fleming Andy-AFLEMING; linuxppc-
> d...@lists.ozlabs.org; Xie Shaohui-B21989
> Subject: RE: SATA FSL and upstreaming
On Thu, 2013-05-16 at 06:48 +, Bhushan Bharat-R65777 wrote:
> 1) Load RCW as Tiejun on some address in DDR.
>
> 2) Brun RCW at 0xec00:
> protect off 0xec00 +$filesize; erase 0xec00 +$filesize; cp.b
> 0x100 0xec00 $filesize
Done.
> 3) run " pix altbak" command
>
> 4) ch
On Thu, 2013-05-16 at 06:49 +, Zang Roy-R61911 wrote:
>
> Please also provide a RCW binary to Ben, if your guys insist updating the
> RCW.
right, I just noticed it's ascii :-) That isn't going to work well...
Cheers,
Ben.
___
Linuxppc-dev mail
On 05/16/2013 02:53 PM, Benjamin Herrenschmidt wrote:
On Thu, 2013-05-16 at 06:49 +, Zang Roy-R61911 wrote:
Please also provide a RCW binary to Ben, if your guys insist updating the RCW.
right, I just noticed it's ascii :-) That isn't going to work well...
Ben,
I already send my wo
Ok, so I found this one on the SDK ISO: rcw_15g_2000mhz.bin
I flashed that, did pix altbank, I'm now booted from Bank 4 ... and PCIe
is still showing nothing. I have cards in slots 4 and 7 (assuming that's
the right numbering, ie, 7 is the top one).
Are we sure we don't have a problem with some D
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