On Thu, 2013-05-16 at 06:17 +0000, Zang Roy-R61911 wrote: > Do you try slot7? > PCIe1 connects to slot7 directly.
I tried all slots. None of them sees any card. The card also doesn't seem to be powered up (none of the LEDs blink, it's an e1000 since I don't have networking with upstream). I also tried a different card and uboot is pretty adamant at saying "no link" :-) I'll try to update the RCW when I know how to do it :-) Cheers, Ben. > Roy > > > -----Original Message----- > > From: Benjamin Herrenschmidt [mailto:b...@kernel.crashing.org] > > Sent: Thursday, May 16, 2013 2:09 PM > > To: Zang Roy-R61911 > > Cc: Bhushan Bharat-R65777; Liu Qiang-B32616; Fleming Andy-AFLEMING; > > linuxppc-dev@lists.ozlabs.org; Xie Shaohui-B21989 > > Subject: Re: SATA FSL and upstreaming > > > > On Thu, 2013-05-16 at 06:05 +0000, Zang Roy-R61911 wrote: > > > I do not suggest changing the RCW. If the RCW is broken on Ben's side, > > > it is not easy to recover for him. > > > Let's check the U-boot output first. > > > > U-Boot 2013.01-00009-g7bcd7f4 (Mar 14 2013 - 14:23:16) > > > > CPU0: P5020E, Version: 1.0, (0x82280010) > > Core: E5500, Version: 1.0, (0x80240010) > > Clock Configuration: > > CPU0:2000 MHz, CPU1:2000 MHz, > > CCB:800 MHz, > > DDR:666.667 MHz (1333.333 MT/s data rate) (Asynchronous), LBC:100 > > MHz > > FMAN1: 600 MHz > > QMAN: 400 MHz > > PME: 400 MHz > > L1: D-cache 32 kB enabled > > I-cache 32 kB enabled > > Board: P5020DS, Sys ID: 0x1c, Sys Ver: 0x12, FPGA Ver: 0x05, vBank: 0 > > Reset Configuration Word (RCW): > > 00000000: 0c540000 00000000 1e120000 00000000 > > 00000010: d8984a01 03002000 de800000 41000000 > > 00000020: 00000000 00000000 00000000 10070000 > > 00000030: 00000000 00000000 00000000 00000000 > > SERDES Reference Clocks: Bank1=100Mhz Bank2=125Mhz Bank3=125Mhz > > I2C: ready > > SPI: ready > > DRAM: Initializing....using SPD > > Detected UDIMM i-DIMM > > Detected UDIMM i-DIMM > > 2 GiB left unmapped > > 4 GiB (DDR3, 64-bit, CL=9, ECC on) > > DDR Controller Interleaving Mode: cache line > > DDR Chip-Select Interleaving Mode: CS0+CS1 > > Testing 0x00000000 - 0x7fffffff > > Testing 0x80000000 - 0xffffffff > > Remap DDR 2 GiB left unmapped > > > > POST memory PASSED > > Flash: 128 MiB > > L2: 512 KB enabled > > Corenet Platform Cache: 2048 KB enabled > > SRIO1: disabled > > SRIO2: disabled > > NAND: 1024 MiB > > MMC: FSL_SDHC: 0 > > EEPROM: NXID v1 > > PCIe1: Root Complex, no link, regs @ 0xfe200000 > > PCIe1: Bus 00 - 00 > > PCIe2: disabled > > PCIe3: Root Complex, no link, regs @ 0xfe202000 > > PCIe3: Bus 01 - 01 > > PCIe4: disabled > > In: serial > > Out: serial > > Err: serial > > Net: Initializing Fman > > Fman1: Uploading microcode version 106.1.7 > > PHY reset timed out > > PHY reset timed out > > PHY reset timed out > > PHY reset timed out > > FM1@DTSEC1, FM1@DTSEC2, FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5, FM1@TGEC1 > > Hit any key to stop autoboot: 0 > > => > > > > Cheers, > > Ben. > > > > > _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
