On Tue, May 26, 2015 at 06:01:03PM -0700, Andy Lutomirski wrote:
> https://chromium-review.googlesource.com/#/c/205161/
>
> Oddly, Coreboot seems to have mis-spelled that MSR. It's
> MSR_PKG_CST_CONFIG_CONTROL, and bit 31 isn't defined in the SDM
> (unsurprisingly).
Since this MSR is a control M
On Wed, May 20, 2015 at 10:48 PM, Andy Lutomirski wrote:
> On May 20, 2015 6:34 PM, "Andy Lutomirski" wrote:
>> If we did that *and* we had a non-crappy mwaitx, then we could apply an
>> optimization: when going idle, we could turn off the TSC deadline timer and
>> use mwaitx instead. This wou
* Huang Rui wrote:
> No, the timeout value doesn't decide how 'deep' the power state
> enters. Basically, the same power consumption with any timeout.
>
> I summarized the comparison of mwait and mwaitx
>
> MWAIT MWAITX
> opcode 0f 01 c9
On Wed, May 20, 2015 at 07:11:20PM +0800, Ingo Molnar wrote:
>
> * Borislav Petkov wrote:
>
> > On Wed, May 20, 2015 at 12:22:58PM +0200, Ingo Molnar wrote:
> >
> > > Well, HLT does not get any hint from the OS how long the idling is
> > > expected to last.
> >
> > MWAIT on AMD doesn't either:
On Thu, 21 May 2015, Borislav Petkov wrote:
> On Thu, May 21, 2015 at 10:56:32PM +0800, Huang Rui wrote:
> > Looks like good use case. Boris, could we try to implement it?
>
> Andy had some suggestions on how to do it here:
>
> https://lkml.kernel.org/r/555d3629.8080...@kernel.org
>
> which sho
On Thu, May 21, 2015 at 10:08 AM, Borislav Petkov wrote:
> On Thu, May 21, 2015 at 09:45:10AM -0700, Andy Lutomirski wrote:
>> I must be missing something. In this sequence, you're sleeping with
>> IF=0 and ECX[0] = 0, so an IRQ won't get handled. Don't we want
>> ECX[0] = 1?
>
> Hmm, so actuall
On Thu, May 21, 2015 at 09:45:10AM -0700, Andy Lutomirski wrote:
> I must be missing something. In this sequence, you're sleeping with
> IF=0 and ECX[0] = 0, so an IRQ won't get handled. Don't we want
> ECX[0] = 1?
Hmm, so actually we don't want to sleep with interrupts disabled. If
ECX[0]=1b, t
On Thu, May 21, 2015 at 9:02 AM, Borislav Petkov wrote:
> On Thu, May 21, 2015 at 10:56:32PM +0800, Huang Rui wrote:
>> Looks like good use case. Boris, could we try to implement it?
>
> Andy had some suggestions on how to do it here:
>
> https://lkml.kernel.org/r/555d3629.8080...@kernel.org
>
> w
On Thu, May 21, 2015 at 10:56:32PM +0800, Huang Rui wrote:
> Looks like good use case. Boris, could we try to implement it?
Andy had some suggestions on how to do it here:
https://lkml.kernel.org/r/555d3629.8080...@kernel.org
which should be doable. Also, you'd probably need to set ECX[0]=0b too
On Thu, May 21, 2015 at 04:15:54AM +0800, Borislav Petkov wrote:
> On Wed, May 20, 2015 at 09:12:15PM +0200, Thomas Gleixner wrote:
> > Which would be good enough for mdelay/udelay I think, but we'd need to
> > measure the time spend in MWAITT so we wont return early.
> >
> > Something like this:
On Wed, May 20, 2015 at 07:21:10PM +0800, Borislav Petkov wrote:
> On Wed, May 20, 2015 at 01:11:20PM +0200, Ingo Molnar wrote:
> > - MWAITX takes a 'timeout' parameter, but otherwise behaves exactly
> > like MWAIT: i.e. once idle it won't exit idle on its own
>
> Let me quote the commit me
On Wed, May 20, 2015 at 05:12:13PM +0800, Borislav Petkov wrote:
> On Wed, May 20, 2015 at 10:55:20AM +0200, Ingo Molnar wrote:
> > Does it use it to decide how 'deep' a sleep it will go into, i.e.
> > larger timeouts cause longer entry and exit latencies?
>
> That's what the HLT thing does. Core
On Tue, May 19, 2015 at 01:31:21PM +0200, Borislav Petkov wrote:
> On Tue, May 19, 2015 at 04:01:10PM +0800, Huang Rui wrote:
> > MWAITX/MWAIT does not let the cpu core go into C1 state on AMD processors.
> > The cpu core still consumes less power while waiting, and has faster exit
> > from waiting
On Wed, 20 May 2015, Andy Lutomirski wrote:
> John, Peter, Thomas: would it actually make sense to teach the core
> timer/clockevent code about perfect time sources like invariant TSC + TSC
Perfect? There is no such concept in timer land.
> deadline? AFAICT right now we're not doing anything par
On May 20, 2015 6:34 PM, "Andy Lutomirski" wrote:
> If we did that *and* we had a non-crappy mwaitx, then we could apply an
> optimization: when going idle, we could turn off the TSC deadline timer and
> use mwaitx instead. This would about an interrupt if the event that wakes us
> is our time
On 05/19/2015 01:01 AM, Huang Rui wrote:
MWAITX/MWAIT does not let the cpu core go into C1 state on AMD processors.
The cpu core still consumes less power while waiting, and has faster exit
from waiting than "Halt". This patch implements an interface using the
kernel parameter "idle=" to configur
On Wed, May 20, 2015 at 09:12:15PM +0200, Thomas Gleixner wrote:
> Which would be good enough for mdelay/udelay I think, but we'd need to
> measure the time spend in MWAITT so we wont return early.
>
> Something like this:
Yeah, with a check maybe:
> delay = usec_to_tsc(delay_usec);
On Wed, 20 May 2015, Borislav Petkov wrote:
> On Wed, May 20, 2015 at 04:55:58PM +0100, One Thousand Gnomes wrote:
> > > That's not what appears to be happening here though: the MWAITX will
> > > return after the timeout.
> > >
> > > Which isn't really useful unless we use it to drive timers.
>
On Wed, May 20, 2015 at 04:55:58PM +0100, One Thousand Gnomes wrote:
> > That's not what appears to be happening here though: the MWAITX will
> > return after the timeout.
> >
> > Which isn't really useful unless we use it to drive timers.
>
> What about things like mdelay() ?
It has an upper l
> That's not what appears to be happening here though: the MWAITX will
> return after the timeout.
>
> Which isn't really useful unless we use it to drive timers.
What about things like mdelay() ?
Alan
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* Thomas Gleixner wrote:
> On Wed, 20 May 2015, Ingo Molnar wrote:
> > * Borislav Petkov wrote:
> >
> > > On Wed, May 20, 2015 at 01:11:20PM +0200, Ingo Molnar wrote:
> > > > - MWAITX takes a 'timeout' parameter, but otherwise behaves exactly
> > > > like MWAIT: i.e. once idle it won't
On Wed, 20 May 2015, Ingo Molnar wrote:
> * Borislav Petkov wrote:
>
> > On Wed, May 20, 2015 at 01:11:20PM +0200, Ingo Molnar wrote:
> > > - MWAITX takes a 'timeout' parameter, but otherwise behaves exactly
> > > like MWAIT: i.e. once idle it won't exit idle on its own
> >
> > Let me quo
* Borislav Petkov wrote:
> On Wed, May 20, 2015 at 01:11:20PM +0200, Ingo Molnar wrote:
> > - MWAITX takes a 'timeout' parameter, but otherwise behaves exactly
> > like MWAIT: i.e. once idle it won't exit idle on its own
>
> Let me quote the commit message:
>
> "MWAITT, another name is
On Wed, May 20, 2015 at 01:11:20PM +0200, Ingo Molnar wrote:
> - MWAITX takes a 'timeout' parameter, but otherwise behaves exactly
> like MWAIT: i.e. once idle it won't exit idle on its own
Let me quote the commit message:
"MWAITT, another name is MWAITX (MWAIT with extensions), has a
conf
* Borislav Petkov wrote:
> On Wed, May 20, 2015 at 12:22:58PM +0200, Ingo Molnar wrote:
>
> > Well, HLT does not get any hint from the OS how long the idling is
> > expected to last.
>
> MWAIT on AMD doesn't either:
Yeah, MWAIT clearly doesn't, but I was talking about MWAITX, which
takes a t
On Wed, May 20, 2015 at 12:22:58PM +0200, Ingo Molnar wrote:
> Well, HLT does not get any hint from the OS how long the idling is
> expected to last.
MWAIT on AMD doesn't either:
"EAX specifies optional hints for the MWAIT instruction. There are
currently no hints defined and all bits should be 0
* Borislav Petkov wrote:
> On Wed, May 20, 2015 at 10:55:20AM +0200, Ingo Molnar wrote:
> > Does it use it to decide how 'deep' a sleep it will go into, i.e.
> > larger timeouts cause longer entry and exit latencies?
>
> That's what the HLT thing does. Cores go into C1 and then at some
> poin
On Wed, May 20, 2015 at 10:55:20AM +0200, Ingo Molnar wrote:
> Does it use it to decide how 'deep' a sleep it will go into, i.e.
> larger timeouts cause longer entry and exit latencies?
That's what the HLT thing does. Cores go into C1 and then at some point
(hysteresis, etc) the whole core comple
* Borislav Petkov wrote:
> On Tue, May 19, 2015 at 04:01:10PM +0800, Huang Rui wrote:
> > MWAITX/MWAIT does not let the cpu core go into C1 state on AMD processors.
> > The cpu core still consumes less power while waiting, and has faster exit
> > from waiting than "Halt". This patch implements a
On Tue, May 19, 2015 at 04:01:10PM +0800, Huang Rui wrote:
> MWAITX/MWAIT does not let the cpu core go into C1 state on AMD processors.
> The cpu core still consumes less power while waiting, and has faster exit
> from waiting than "Halt". This patch implements an interface using the
> kernel param
MWAITX/MWAIT does not let the cpu core go into C1 state on AMD processors.
The cpu core still consumes less power while waiting, and has faster exit
from waiting than "Halt". This patch implements an interface using the
kernel parameter "idle=" to configure mwaitx type and timer value.
If "idle=mw
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