On Wed, May 20, 2015 at 10:48 PM, Andy Lutomirski <l...@amacapital.net> wrote: > On May 20, 2015 6:34 PM, "Andy Lutomirski" <l...@kernel.org> wrote: >> If we did that *and* we had a non-crappy mwaitx, then we could apply an >> optimization: when going idle, we could turn off the TSC deadline timer and >> use mwaitx instead. This would about an interrupt if the event that wakes >> us is our timer. >> > > Hey, Intel, want to document your secret "Timed MWAIT" feature? It > causes a transition to C0 when the deadline expires (see 4.2.4 of the > Desktop 4th Generation Intel Core Processor Family Datasheet Volume 1, > order number 328897-001) and it even has an erratum (HSD63 / BDM32), > but the instruction itself doesn't appear to be documented. >
Found more: https://chromium-review.googlesource.com/#/c/205161/ Oddly, Coreboot seems to have mis-spelled that MSR. It's MSR_PKG_CST_CONFIG_CONTROL, and bit 31 isn't defined in the SDM (unsurprisingly). --Andy -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
