* Borislav Petkov <b...@suse.de> wrote:
> On Tue, May 19, 2015 at 04:01:10PM +0800, Huang Rui wrote:
> > MWAITX/MWAIT does not let the cpu core go into C1 state on AMD processors.
> > The cpu core still consumes less power while waiting, and has faster exit
> > from waiting than "Halt". This patch implements an interface using the
> > kernel parameter "idle=" to configure mwaitx type and timer value.
> >
> > If "idle=mwaitx", the timeout will be set as the maximum value
> > ((2^64 - 1) * TSC cycle).
> > If "idle=mwaitx,100", the timeout will be set as 100ns.
> > If the processor doesn't support MWAITX, then halt is used.
So what does the hardware do with the timeout value?
Does it use it to decide how 'deep' a sleep it will go into, i.e.
larger timeouts cause longer entry and exit latencies?
Or some other purpose?
I suppose it's also the case that if an interrupt arrives _before_ the
expected timeout then MWAITX will try to exit immediately, it won't
wait until the timeout, right?
Thanks,
Ingo
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