On Tue, May 26, 2015 at 06:01:03PM -0700, Andy Lutomirski wrote:
> https://chromium-review.googlesource.com/#/c/205161/
>
> Oddly, Coreboot seems to have mis-spelled that MSR. It's
> MSR_PKG_CST_CONFIG_CONTROL, and bit 31 isn't defined in the SDM
> (unsurprisingly).
Since this MSR is a control MSR and from looking at the comment in the
coreboot code and how they set that bit, it enables that MWAIT variant.
Even if the MSR write would stick on your hw, though, you'd still need
to know what it takes into EAX/ECX (and possibly some other register...
EBX, EDX...?) It might bring you some fun while trying to figure it out
:-)
--
Regards/Gruss,
Boris.
ECO tip #101: Trim your mails when you reply.
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