Hi, all,
This issue has not been fixed yet. Can anyone suggest how to fix this?
To deal with the invalid address, I tried to define a new python class, PIOBus,
inherent
from Noncoherent bus and the new python class contains BadAddr member, like the
way used in
classic memory system. Then I use
Hi, All
I am try to compile x86 ISA with command: scons -j4
build/X86_MESI_CMP_directory/gem5.opt RUBY=true SLICC_HTML=true .
However, I encountered the following error:
[ CXX] X86_MESI_CMP_directory/arch/x86/generated/timing_simple_cpu_exec.cc
-> .o
[SO PARAM] OpDesc -> X86_MESI_CMP_d
I have solved the problem. The reason is that the compilation ran out of memory.
From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On
Behalf Of GE ZHIGUO
Sent: Monday, May 13, 2013 9:44 AM
To: gem5 users mailing list
Subject: [gem5-users] x86 ISA compilation error
Hi, All
Hi, Amit
I think that you should use configs/example/ruby_fs.py instead of fs.py.
But ARM detailed CPU does not work with Ruby for full system simulation so far.
Regards,
Zhiguo
From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On
Behalf Of Amit Tara
Sent: Thursday, Ju
Hi, All
I am trying to run SMT/ARM O3CPU, however, segmentation fault happened
when running two hello programs in 2 SMT in ARM/O3CPU.
I debugged using GDB and found that the problem is caused in:
-
DefaultCommit::squashAll(ThreadID tid)
{
// If we want to include the squa
Hi,
Is it possible for GEM5 to run an application with little endian
instructions and big endian data?
If I want to achieve this, which codes in GEM5 should I touch? I read the
source codes for some time,
however, I cannot get clear clues .
Thanks!
__
Hi,
I found that the TLB implementation in SE mode is much different from that
in full system mode.
There is actually no real TLB in SE. I am curious why TLB is so different in
GEM5 SE mode.
Is there anything that prevents us from using TLB in SE? Can we implement TLB
in SE mode?
Thanks!
tlb (and have table walks) you would need to create a complete
page table. While doable, FS mode provides this if you want to use it.
Ali
On Aug 4, 2013, at 11:41 PM, GE ZHIGUO
mailto:ge.zhi...@huawei.com>> wrote:
Hi,
I found that the TLB implementation in SE mode is much differen
that
all the required processor registers aren't appropriately initialized to do a
table walk in SE mode, so that would need to be fixed too. Why not run in FS
mode?
Ali
On Aug 5, 2013, at 12:04 AM, GE ZHIGUO
mailto:ge.zhi...@huawei.com>> wrote:
Hi, Ali
Thanks!
To enabl
Hi,
I have a question about O3CPU pipeline in GEM5.
My understanding about the GEM5 O3CPU is that rename stage does not put
instructions
into instruction queue(issue queue) and ROB. Dispatch stage actually does the
above. So, rename + dispatch in GEM5 is actually the rename stage of O3CPU.
Pl
01CE0E9A.2B553540] Visit us at:
Facebook<https://www.facebook.com/AMD> | amd.com<http://www.amd.com/>
-Original Message-
From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On
Behalf Of GE ZHIGUO
Sent: Wednesday, August 14, 2013 11:59 AM
To: gem5 users mailing li
sers-boun...@gem5.org<mailto:gem5-users-boun...@gem5.org>
[mailto:gem5-users-boun...@gem5.org<mailto:gem5-users-boun...@gem5.org>] On
Behalf Of GE ZHIGUO
Sent: Wednesday, August 14, 2013 11:59 AM
To: gem5 users mailing list
Subject: [gem5-users] About the rename and dispatch stages in O3CP
Hi,
Can anyone help?
transitions_per_cycle parameter can be used to specify the bandwidth. However,
the cache access hit and miss cannot be distinguished. In addition cache read
and write can not be
distinguished either. The default value of transitions_per_cycle is 32 which is
too large for c
Hi, Korey
Whether are you going to submit the patch recently?
I am going to enable ARM/InOrder CPU model.
Can you please provide help and guidances when I do the enabling?
Thanks and best regards,
Zhiguo
From: gem5-users-boun...@gem5.org [gem5-use
Hi, Korey
Thanks a lot for offering help!
Look forward to your advices.
Best regards,
Zhiguo
From: koreylsew...@gmail.com [koreylsew...@gmail.com] on behalf of Korey Sewell
[ksew...@umich.edu]
Sent: Friday, August 30, 2013 2:13 AM
To: GE ZHIGUO
Cc
From: koreylsew...@gmail.com [koreylsew...@gmail.com] on behalf of Korey Sewell
[ksew...@umich.edu]
Sent: Friday, August 30, 2013 2:13 AM
To: GE ZHIGUO
Cc: gem5 users mailing list
Subject: Re: [gem5-users] ARM InOrder implement
Hi Zhiguo,
I marked this email for
forward to your advices!
Thanks and regards!
Zhiguo
From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On
Behalf Of GE ZHIGUO
Sent: Friday, August 30, 2013 5:00 PM
To: Korey Sewell
Cc: gem5 users mailing list
Subject: Re: [gem5-users] ARM InOrder implement
Hi, Korey
May I ask
isIndirectCtrl() in base_dyn_inst.hh?
From: koreylsew...@gmail.com [mailto:koreylsew...@gmail.com] On Behalf Of Korey
Sewell
Sent: Thursday, September 12, 2013 2:23 PM
To: GE ZHIGUO
Cc: gem5 users mailing list
Subject: Re: [gem5-users] ARM InOrder implement
[inline]
1. For InorderCPU, as the
Hi,
ARM ldrex instruction use LoadLockedReq (mem/packet.cc) in GEM5.
If I am not wrong, according to ARM document, ldrex will make cache line in
exclusive state.
But LoadLockedReq does NOT have NeedsExclusive attribute now.
does LoadLockedReq packet miss NeedsExclusive attribute or should ldrex
e when the store
is sent to the caches).
Ali
On Sep 20, 2013, at 12:30 AM, GE ZHIGUO
mailto:ge.zhi...@huawei.com>> wrote:
Hi,
ARM ldrex instruction use LoadLockedReq (mem/packet.cc) in GEM5.
If I am not wrong, according to ARM document, ldrex will make cache line in
exclusive state.
B
Hi,
I encountered the same problem. Anyone have figured this out?
I guess that blocksInUse() should be per hardware thread in SMT.
Thanks!
From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On
Behalf Of Yuval H. Nacson
Sent: Friday, May 25, 2012 1:19 AM
To: 'gem5 users mailin
Hi, Alex
I think that it is Miss-Status Handling Registers (MSHR) in cache.
Regards
Zhiguo
From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On
Behalf Of Alex Tomala
Sent: Wednesday, October 02, 2013 8:07 AM
To: gem5-users@gem5.org
Subject: [gem5-users] What is the TBE in R
ut LoadLockReq packet attribute
StoreConditional has NeedsExclusive set. Can you provide any more details about
the bug?
Ali
On 29.09.2013 23:58, GE ZHIGUO wrote:
Hi, Ali
Thanks!
Yes, I added NeedsExclusive attribute to LoadLockedReq, and then it works.
I also had thought that Store condit
...@arm.com]
Sent: Tuesday, October 08, 2013 12:02 AM
To: gem5-users@gem5.org
Cc: GE ZHIGUO; sa...@umich.edu
Subject: Re: [gem5-users] About LoadLockReq packet attribute
Hi,
you need to properly order the lock acquisition with the counter
manipulations, for example as below (or see
http://lxr.free
state.
Is this statement correct?
Thanks!
Zhiguo
-Original Message-
From: GE ZHIGUO
Sent: Tuesday, October 08, 2013 11:34 AM
To: 'Stephan Diestelhorst'; gem5-users@gem5.org
Cc: sa...@umich.edu
Subject: RE: [gem5-users] About LoadLockReq packet attribute
Hi,Stephan
Thanks for
Have you specify the destinations(i.e., L3 cache node) correctly when sending
the messages?
-Original Message-
From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On
Behalf Of Naranjo Carmona, Alberto Javier
Sent: Thursday, October 10, 2013 11:11 AM
To: gem5 users mai
You need to modify exitGroupFunc() in sim/syscall_emul.cc NOT to exit simloop
before all running contexts finish.
Good luck!
Zhiguo
From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On
Behalf Of Yuan Yao
Sent: Monday, October 21, 2013 2:00 PM
To: gem5 users mailing list
S
Yes, it supports if I did not misunderstanding GEM5 source code.
This is a very basic functionality of store queue.
Anyone please correct me if I am wrong. Thanks!
Zhiguo
-Original Message-
From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On
Behalf Of Yuan Yao
Sen
Hi, All
How TLB works under GEM5/SMP and SMT, for example TLB shootdown, TLB sharing
under SMT, etc?
Can we simply disable TLB in FS mode? From functionality perspective, it should
be ok, but
I am not sure whether it works for FS related to security attributes.
Thanks!
Zhiguo
_
Hi, Vanchi
There is a component which is responsible for register mapping in O3CPU.
You can look into that part of codes.
Regards,
Zhiguo
From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On
Behalf Of Vanchinathan Venkataramani
Sent: Thursday, January 02, 2014 1:47 PM
To: g
Hi, Zhaoxia,
I experienced the same problem.
You can work around it using checkpoint.
Regards,
Zhiguo
-Original Message-
From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On
Behalf Of Zhaoxia Deng
Sent: Wednesday, January 22, 2014 7:13 AM
To: gem5 users mailing lis
Can you increase the cache size so that the cache miss rate is within 8% to see
whether
direct map cache still has lower cache miss rate?
Zhiguo
-Original Message-
From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On
Behalf Of Summer
Sent: Wednesday, February 12, 2
Behalf Of AKT
Sent: Friday, February 21, 2014 5:23 AM
To: gem5-users@gem5.org
Subject: Re: [gem5-users] GEM5 run with PARSEC blackscholes - Seems to be early
termination
Hello Udit, GE ZHIGUO,
I am seeing same type of output with PARSEC while running and it is
completed in 15 min. same as Udit
Hi, Zhao Hui
To my knowledge, Ruby supplies data to CPU and I remember that ruby writes data
to cache.
Thus, If I am not wrong, the program execution output SHOULD probably produces
wrong outputs if there is problem with cache protocol modeled by ruby.
Regards,
Zhiguo
From: gem5-users-boun...@g
Hi, All
In GEM5, there is a separate InOrderCPU model which is not as well as supported
as O3CPU.
My question is why not modify the dispatch/issue part of O3CPU to emulate an
InOrderCPU?
Are there any issues to affect the accuracy of InOrderCPU model by making the
O3CPU issuing the instructions
r have fetch and issue width 2.. Intel atom does not have a
load store queue...but load store queue entries could be made to have same as
Rob..increasing entries in lsq will not have any effect in performance unless
entries in Rob have increased..
On Mar 10, 2014 5:18 AM, "GE ZHIGUO"
mail
Has anyone used Ruby on ARM FS?
Thanks!
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o 256MB of physical memory starting
at address 0, then there are 64MB set aside for the bootloader starting at
address 2GB. As of yet, there haven't been any emails regarding a fix or
work-around for this.
-Andrew
On Fri, May 11, 2012 at 1:03 AM, GE ZHIGUO
mailto:ge.zhi...@huawei.com>> w
Hi, I ran blackscholes in PARSEC Benchmark using GEM5 FS Alpha. However, the
execution results are not correct.
I tried configurations of 4 processors, 1 processors, and Ruby, non Ruby. The
outputs are the same which is not right.
When executing the benchmark, there are some warnings like:
warn:
Hi, Udit
You might use a too big number of fast forwarding(-F 500).
Try to use -F 5000.
Regards,
Zhiguo
-Original Message-
From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On
Behalf Of Udit Kumar
Sent: Tuesday, June 05, 2012 2:31 PM
To: gem5 users ma
5/12, GE ZHIGUO wrote:
> Hi, Udit
> You might use a too big number of fast forwarding(-F 500).
> Try to use -F 5000.
>
> Regards,
> Zhiguo
>
> -Original Message-
> From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On
> Behalf O
Hi, All,
I would like to run multi-instance of full system simulation of GEM5.
Is there any interferences as the multi-instance need to use the same linux
image file?
Thanks!
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gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin
I run simulation with GEM5/Ruby. And I got the following statistics from
stats.txt and ruby.stats:
If I am not wrong, the sim_ticks in stats.txt and Ruby_cycles in ruby.stats
should be almost the same.
But in my simulation, they are much different. Can anyone help interpret the
data? Thanks!
St
Hi,
I run simulation with GEM5/Ruby. And I got the following statistics from
stats.txt and ruby.stats:
If I am not wrong, the sim_ticks in stats.txt and Ruby_cycles in ruby.stats
should be almost the same.
But in my simulation, they are much different. Can anyone help interpret the
data? Thanks!
I would like to model a system with multiple processors and each processor has
multiple cores using GEM5/Ruby.
How to do this and any examples exist? Thanks!
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gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-
Hi,
I run simulation with GEM5/Ruby. And I got the following statistics from
stats.txt and ruby.stats:
If I am not wrong, the sim_ticks in stats.txt and Ruby_cycles in ruby.stats
should be almost the same.
But in my simulation, they are much different. Can anyone help interpret the
data? Thanks!
: gem5-users-boun...@gem5.org [gem5-users-boun...@gem5.org] on behalf of
Nilay [ni...@cs.wisc.edu]
Sent: Wednesday, June 13, 2012 4:04 AM
To: gem5 users mailing list
Subject: Re: [gem5-users] How to interprete Ruby_cycles in the simulation
results of Ruby
On Tue, June 12, 2012 5:18 am, GE ZHIGUO
Hi, Is there any tool to convert SLICC description to FSM diagram directly.
Thanks!
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FSM diagram
take a look at graphviz, using a little bit of scripting, you might be able to
generated the desired FSM.
On Thu, Jun 14, 2012 at 7:27 AM, Nilay Vaish
mailto:ni...@cs.wisc.edu>> wrote:
On Thu, 14 Jun 2012, GE ZHIGUO wrote:
Hi, Is there any tool to convert SLICC description
Hi, All,
I know that GEM5 can generate html files from SLICC files. But I have
not figured out how to do that.
Can anyone tell me? Thanks!
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In the file MOESI_hammer-cache.sm, should the following transition be changed
to a more suitable transition?
transition(MM, Other_GETS, I) {
c_sendExclusiveData;
l_popForwardQueue;
}
The above transition should be:
transition(MM, Other_GETS, O) {
ee_sendDataShared;
l_popFo
In the file MOESI_hammer-cache.sm, should the following transition be changed?
transition(MM, Other_GETS, I) {
c_sendExclusiveData;
l_popForwardQueue;
}
The above transition should be changed to:
transition(MM, Other_GETS, O) {
ee_sendDataShared;
l_popForwardQueue;
}
Th
In the file MOESI_hammer-cache.sm, should the following transition be changed?
transition(MM, Other_GETS, I) {
c_sendExclusiveData;
l_popForwardQueue;
}
The above transition should be changed to:
transition(MM, Other_GETS, O) {
ee_sendDataShared;
l_popForwardQueue;
}
T
It seems that the output file in full system GEM5 is a ram file which will not
be written to linux.img.
Due to this, I cannot get the file after I exit gem5 simulation environment.
Thanks!
Zhiguo
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http://m
BBench-ICS disk image. Check out this
link:
http://gem5.org/Bbench-gem5#Tips_for_Making_Your_Disk_Image_gem5_Friendly
-Tony
On Sun, Jul 15, 2012 at 11:15 PM, GE ZHIGUO
mailto:ge.zhi...@huawei.com>> wrote:
It seems that the output file in full system GEM5 is a ram file which will not
be w
You cannot see the output file when GEM5 using a extra file layer in which the
output file will not be written to disk file.
By running application in the linux on GEM5 directly instead of running script,
You can specify the output file and use cat command to check the output.
Regards,
Zhiguo
F
ossible. You need to remove the copy-on-write
layer. I did this when developing the BBench-ICS disk image. Check out this
link:
http://gem5.org/Bbench-gem5#Tips_for_Making_Your_Disk_Image_gem5_Friendly
-Tony
On Sun, Jul 15, 2012 at 11:15 PM, GE ZHIGUO
mailto:ge.zhi...@huawei.com>> wrote:
It
It works now. The problem seems due to application execution problem.
Thanks!
Zhiguo
From: GE ZHIGUO
Sent: Tuesday, July 17, 2012 1:07 PM
To: gem5 users mailing list
Subject: RE: [gem5-users] Is it possible to write the output file of an
application into linux.img when full system gem5 runs
Hi, All
A SLICC component uses message buffer to receive and send messages. If I
am not wrong,
A message buffer will be connected to peer message buffers in other
components via interconnection network.
My question is how this connection(a message buffer peer) is specified in SLICC
file?
Hi, I am trying to simulate MOESI_CMP_directory protocol.
But I cannot find out how to specify the parameters of ProcsPerChip.
Can anyone advice? Thanks!
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Hi, All
The L1 and L2 caches are connected via Interconnections. I specify the
latency of the transitions in SLICC file to 1 cycle when L1 send message to L2.
But still the latency of the message delivery can be many more than 1 cycle.
My question is how to specify the latency between L1
contention.
- Tushar
On Sep 11, 2012, at 1:10 AM, GE ZHIGUO wrote:
Hi, All
The L1 and L2 caches are connected via Interconnections. I specify the
latency of the transitions in SLICC file to 1 cycle when L1 send message to L2.
But still the latency of the message delivery can be many more than
protocol_L1cache.sm
and protocol_L2cache.sm
The cache.sm file contains both L1 and L2, modeling a fixed delay between them.
Each "cache" is then connected to other "caches" via the network.
cheers,
Tushar
On Sep 11, 2012, at 9:13 PM, GE ZHIGUO wrote:
Hi, Tushar
Thank
communicate via
a similar manner for inclusive. Since both L1 and L2 are data structures within
the same file, I don't think you need a "queue" to communicate between them in
the code.
- Tushar
On Sep 11, 2012, at 10:28 PM, GE ZHIGUO wrote:
Hi, Tushar
I also thought of us
Hi, I have the same problem.
You can run the benchmark on desktop to get the correct results. Or you run the
benchmark using class memory model
In stead of ruby model.
Regards,
Zhiguo
From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On
Behalf Of Mostafa Mahmoud Hassan
Sent
list
Subject: Re: [gem5-users] How to specify the latency between L1 and L2 cache
Ah ...
Hmm yeah you'll have to see if it is easier to have 2 separate files then, or
just have one file with extra states.
On Sep 11, 2012, at 10:58 PM, GE ZHIGUO wrote:
In exclusive cache, each address
the classic memory model gives the right results, but Ruby
does not? Which Ruby protocol are you using? It could be that the Alpha LL/SC
synchronization operations are not implemented properly in some of the Ruby
protocols.
Steve
On Tue, Sep 11, 2012 at 8:00 PM, GE ZHIGUO
mailto:ge.zhi
Hi, All
I use zz_stallAndWaitRequest to stall and wait a messag in a busy state.
And when the busy state transits to a stable state, I use
ka_wakeUpAllDependents to wakeup
All the messages that are waiting in the waiting table. In most cases,
The waiting message can be woken up. However, som
Hi, All
Does Ruby/SLICC support atomic operation?
I found that atomic is treated as Store in MOESI_hammer and MESI_CMP_directory
example protocols.
But I think this approach may cause live lock when two processors try to do
atomic to the same cache line and each one
Interrupt the other. C
2:49 AM
To: GE ZHIGUO
Cc: gem5 users mailing list
Subject: Re: [gem5-users] Does Ruby support Atomic operation
On Fri, 19 Oct 2012, GE ZHIGUO wrote:
> Hi, All
>
> Does Ruby/SLICC support atomic operation?
As I understand, Ruby supports load linked / store conditional memory
operat
Hi,
Can you figure out the source code which causes this problem.
I encountered a similar problem due to live-lock caused because two cores call
Load linked/Store conditional.
I hacked the problem by set the latency between CPU and L1 cache from 3 to 1
cycle.
I am interested in your case and p
You might want to try this.
http://www.capsl.udel.edu/splash/
Regards,
From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On
Behalf Of Veydan Wu
Sent: Wednesday, October 24, 2012 10:14 PM
To: gem5-users@gem5.org
Subject: [gem5-users] look for runnable splash2
Hi, all,
I tr
d and passed the test on native machine.
But the ALPHA version of splash2 (Ocean and FFT) failed to run on Gem5 (OOO,
with cache). There are segmentation fault. Have you encountered this before?
Thanks.
Weidan
On Wed, Oct 24, 2012 at 11:54 PM, GE ZHIGUO
mailto:ge.zhi...@huawei.com>> wrote
Hi,
load instruction is written back to memory?? Write back to register?
The load instruction need not to be committed. The add instruction can start to
execute as long as the data of the load instruction is available.
Zhiguo
From: gem5-users [mailto:gem5-users-boun...@gem5.org] On Behalf Of V
What did you mean by no data written to address A?
From: gem5-users [mailto:gem5-users-boun...@gem5.org] On Behalf Of Vanchinathan
Venkataramani via gem5-users
Sent: Sunday, May 04, 2014 12:06 AM
To: gem5 users mailing list
Subject: [gem5-users] Reading wrong data from Cache
Hi all
I'm looking
from Cache
Since 10 is the last value written to address A, it has to read 10 from address
A.
However it reads value 20 from Address A
On Mon, May 5, 2014 at 11:56 AM, GE ZHIGUO via gem5-users
mailto:gem5-users@gem5.org>> wrote:
What did you mean by no data written to address A?
From: gem5
What did you mean by header and footer code?
GEM5 need to parse and load the binary for execution.
From: gem5-users [mailto:gem5-users-boun...@gem5.org] On Behalf Of Vanchinathan
Venkataramani via gem5-users
Sent: Wednesday, September 17, 2014 5:50 PM
To: gem5 users mailing list
Subject: [gem5-
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