Hi, Ali,
I wrote a program to test mutex implemented using spin_lock under SE mode.
The disassembly codes of the spin_lock are like follows:
LDREX r1, [r0]
CMP r1, #0
BNE RELOAD
STREX r2, r3, [r0]
CMP r2, #0
BNE RELOAD
B LOCK_SUCCESSFUL
I rewrite the GEM5 MMU to map a variable used by two CPUs(in SE mode, i.e., two
programs) to the same
physical address in main memory, so that we have global variable seen by two
CPUs which
can be used to implement the mutex.
Two CPUs keep on doing the followings:
1. call spin_lock to lock the same global variable(mutex)
2. if gain the mutex, increment the value of a counter (a global value
shared by two CPUs)
3. release mutex, and go to step 1 again, until certain number of
iteration reaches.
The program is:
for(int j = 0; j < 100; j++) {
for(int k = 0; k < 100; k++) {
spin_lock(&g_mutex);
counter++;
spin_unlock(&g_mutex);
}
}
I set each CPU does about 10000 iterations and the final value of the counter
should be 20000, however,
The actual number is not 20000, but around 19999, or 19997.
I debugged and found that in some cases, two CPUs can obtain the mutex
simultaneously and both CPUs
enter the critical section. As a sequence, both CPUs increment the counter in
the critical section simultaneously.
I tried to modify the attribute of LDREX to be needsExclusive then, the problem
would disappear.
But I am still confused that the problem should not happen if STREX tries to
obtain exclusive before it does the
actual store.
My guess about the cause of the problem of LDREX/STREX might be:
If we let STREX to obtain exclusive rather than LDREX, we need to implement
global monitor to guarantee the
LDREX/STREX semantics. Otherwise, if we do not have global monitor, we need to
let LDREX to obtain exclusive,
and thus global monitor is not needed.
Best regards,
Zhiguo
From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On
Behalf Of Ali Saidi
Sent: Friday, October 04, 2013 11:39 PM
To: gem5 users mailing list
Subject: Re: [gem5-users] About LoadLockReq packet attribute
StoreConditional has NeedsExclusive set. Can you provide any more details about
the bug?
Ali
On 29.09.2013 23:58, GE ZHIGUO wrote:
Hi, Ali
Thanks!
Yes, I added NeedsExclusive attribute to LoadLockedReq, and then it works.
I also had thought that Store conditional will get exclusive state anyway, so
LoadLockedReq do not need to exclusive access to the cache line.
However, it is not the case currently.
Without NeedsExclusive attribute in LoadLockedReq, two CPUs can store
successfully and thus
both of them can enter to the critical section if spin lock is implemented
through loadlinked/storecontitional.
There might be some bugs in store-conditional logic or implementation in GEM5.
Regards,
Zhiguo
From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On
Behalf Of Ali Saidi
Sent: Monday, September 30, 2013 11:30 AM
To: gem5 users mailing list
Subject: Re: [gem5-users] About LoadLockReq packet attribute
Hi Zhiguo,
There are two concepts here, cache states and the state of a exclusive monitor
(that checks if the cache line has been written since it was put in the
monitor) .While these concepts can be joined, they don't need to be.
So, you could probably add the NeedsExclusive attribute and it should work, but
it doesn't strictly need to (it will get cache exclusive state when the store
is sent to the caches).
Ali
On Sep 20, 2013, at 12:30 AM, GE ZHIGUO
<ge.zhi...@huawei.com<mailto:ge.zhi...@huawei.com>> wrote:
Hi,
ARM ldrex instruction use LoadLockedReq (mem/packet.cc) in GEM5.
If I am not wrong, according to ARM document, ldrex will make cache line in
exclusive state.
But LoadLockedReq does NOT have NeedsExclusive attribute now.
does LoadLockedReq packet miss NeedsExclusive attribute or should ldrex use
another type packet?
Thanks!
Zhiguo
_______________________________________________
gem5-users mailing list
gem5-users@gem5.org<mailto:gem5-users@gem5.org>
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
_______________________________________________
gem5-users mailing list
gem5-users@gem5.org<mailto:gem5-users@gem5.org>
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
_______________________________________________
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
