Hi, Ali Thanks! Yes, I added NeedsExclusive attribute to LoadLockedReq, and then it works.
I also had thought that Store conditional will get exclusive state anyway, so LoadLockedReq do not need to exclusive access to the cache line. However, it is not the case currently. Without NeedsExclusive attribute in LoadLockedReq, two CPUs can store successfully and thus both of them can enter to the critical section if spin lock is implemented through loadlinked/storecontitional. There might be some bugs in store-conditional logic or implementation in GEM5. Regards, Zhiguo From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On Behalf Of Ali Saidi Sent: Monday, September 30, 2013 11:30 AM To: gem5 users mailing list Subject: Re: [gem5-users] About LoadLockReq packet attribute Hi Zhiguo, There are two concepts here, cache states and the state of a exclusive monitor (that checks if the cache line has been written since it was put in the monitor) .While these concepts can be joined, they don't need to be. So, you could probably add the NeedsExclusive attribute and it should work, but it doesn't strictly need to (it will get cache exclusive state when the store is sent to the caches). Ali On Sep 20, 2013, at 12:30 AM, GE ZHIGUO <ge.zhi...@huawei.com<mailto:ge.zhi...@huawei.com>> wrote: Hi, ARM ldrex instruction use LoadLockedReq (mem/packet.cc) in GEM5. If I am not wrong, according to ARM document, ldrex will make cache line in exclusive state. But LoadLockedReq does NOT have NeedsExclusive attribute now. does LoadLockedReq packet miss NeedsExclusive attribute or should ldrex use another type packet? Thanks! Zhiguo _______________________________________________ gem5-users mailing list gem5-users@gem5.org<mailto:gem5-users@gem5.org> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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