Hi, Can anyone help? transitions_per_cycle parameter can be used to specify the bandwidth. However, the cache access hit and miss cannot be distinguished. In addition cache read and write can not be distinguished either. The default value of transitions_per_cycle is 32 which is too large for cache access hit. I think that this can cause significant performance error.
Anyone have any comments and suggestions on this issue and the method to solve this issue? Regards, Zhiguo -----Original Message----- From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On Behalf Of Yuan Yao Sent: Wednesday, August 21, 2013 9:42 PM To: gem5-users@gem5.org Subject: [gem5-users] Requests for the same cacheline in Ruby Hi, all, I try to understand the mechanism Ruby uses to handle the case when a request comes by for the same cacheline to an outstanding request. As I look into the code, Ruby will kind of reject the later request, indicating that "the address is aliased". And the O3CPU gets this response and retries sending the request later. In terms of performance, this implementation is unrealistic for me, since accesses to the same cacheline are serialised, which should be a parallel fashion. For example, if the outstanding request is experiencing a miss (primary miss), then the later one (secondary miss) could be merged into it and gets data simultaneously when the miss completes. Am I missing something? Any help is welcome. Yuan _______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users _______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
