[gem5-users] X86 In Order CPU Model

What is the current level of support for In Order pipeline configuration for X86 in gem5? ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] Definition of "width" in gem5

I have a very basic question, Is width defined in terms of No. of Instructions always? For instance let's say I want to simulate an x86 pipeline with issue width of 8 simple uops/cycle. Should I set issue width as 8 or 4 (fused uops/instructions ) ? ___ g

Re: [gem5-users] Definition of "width" in gem5

Thanks, Fernando. On Tue, Jun 2, 2015 at 4:46 AM, Fernando Endo wrote: > Hello, > > To my understanding, width of pipeline stages is in uops. > > Regards, > > -- > Fernando A. Endo, PhD student and researcher > > Université de Grenoble, UJF > France > >

[gem5-users] QEMU to generate host binary

Is it possible for qemu to generate a binary for whatever application it is emulating, which can later be run directly on host? ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] Instruction trace as input to GEM5

I am using QEMU to generate translated host code, which is just a log of assembly instructions (dumped for each Translation Block). I want to simulate those assembly instructions. How easy is it to do such simulation in gem5? As far as I know there is some sort of support of input traces in gem5.

[gem5-users] TraceGen and instruction execution trace

Hello !! Can traceGen module be used to simulate instruction traces? The tests that are available in gem5 rep. use traceGen module to replace CPU and connect traceGen with mem. Is it possible to use traceGen with CPU and feed instructions to CPU from a trace file? Thanks __

[gem5-users] Hit and Response Latency in Gem5

Hi ! Let's say I have # L1 Cache Hit Latency=2 cycles Response Latency =2 cycles # L2 Cache Hit Latency = 4 cycles Response Latency = 4 cycles # According to my understanding of hit and response latency parameters

[gem5-users] Non-speculative instruction cache misses

correct path instructions. Looking for your help ! -Ayaz Akram ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] simulate multiple binary files in Gem5

Hi, If by simulating multiple binary files, you mean running multiple simulations at the same time you can do that using -d [Directory where output files of simulation should be stored] switch on command line . If you mean running multiple programs in a multicore/multiprocessor system, you can cha

Re: [gem5-users] How to associate stats printings to m5ops in FSmode?

Probably you are seeing too much dumped stats instances because m5ops like dumpresetstats repeat dumping every fixed number of ticks e.g. this is what documentation says about dumpstats : "dumpstats [*delay* [*period*]]: Save simulation statistics to a file in *delay* ticks; repeat this every *per

[gem5-users] Cloudsuite

Hi, all ! I was wondering if anyone has been able to successfully run all cloudsuite [1] benchmarks on gem5 ? [1] http://parsa.epfl.ch/cloudsuite/cloudsuite.html ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinf

[gem5-users] BigDataBench

Has anyone run BigDataBench [1] benchmarks on gem5. I am able to run these benchmarks in functional mode and full system simulation. But simulation gets crashed in detailed mode. Anyone who managed to run them successfully ? [1] http://prof.ict.ac.cn/

[gem5-users] Gem5 inside Gem5

I am trying to run gem5 binary inside gem5 in FS mode. The gem5 binary which is running inside the simulated system crashes with the error : "terminate called after throwing an instance of 'std::bad_alloc' " . I have increased the mem-size from 4 GB to 16 GB, but i am getting the same issue. Can an

Re: [gem5-users] Gem5 inside Gem5

ch faster > > Regards, > > *Renju Boben* > > *M Tech* > > *Electronic Systems* > > *IIT Bombay* > *Ph - 7506112155* > > On Mon, Feb 8, 2016 at 12:16 AM, Ayaz Akram wrote: > >> I am trying to run gem5 binary inside gem5 in FS mode. The gem5 binary >>

[gem5-users] BBV generation through gem5

I am generating BBV file using gem5 for a benchmark in full system mode. Surprisingly the number of simulated instructions when gem5 is run for BBV generation is very different when I run the same benchmark on gem5 in detailed mode. I am running benchmark in both cases from a checkpoint and the ins

Re: [gem5-users] BBV generation through gem5

referably run more than one > experiment so that you can get some statistical rigor. > > Andreas > > From: gem5-users on behalf of Ayaz Akram < > aaq...@gmail.com> > Reply-To: gem5 users mailing list > Date: Tuesday, 23 February 2016 at 06:20 > To: gem5 users maili

Re: [gem5-users] BBV generation through gem5

hat it is entirely > plausible that it has nothing to do with the BBV generation, and is caused > purely by the timing differences. It’s at least something to be mindful of. > > Andreas > > From: gem5-users on behalf of Ayaz Akram < > aaq...@gmail.com> > Reply-To: gem5

[gem5-users] Detailed Mode BBV Generation

Gem5 supports creation of basic block vector profile in atomic mode with fastmem. I have ported the same code to detailed mode so that I can generate basic block vector profile in detailed mode (as in full system mode, I was seeing some differences in execution path in detailed and atomic mode). Th

Re: [gem5-users] Detailed Mode BBV Generation

> There is nothing wrong with it…but the question is why you would do BBV > generation with the o3 CPU? The atomic mode CPU is much faster. Why would > you not just use that? > > Andreas > > From: gem5-users on behalf of Ayaz Akram < > aaq...@gmail.com> > Reply-To: g

[gem5-users] RAS implementation in Gem5

I have a question regarding RAS implementation in gem5. I wonder, why the address of "call instruction" is pushed to RAS instead of address of instruction next to the "call instruction". I am referring to following line of code in "ReturnAddrStack::push(const TheISA::PCState &return_addr)" functi

[gem5-users] Pseudo Instructions (NonSpeculative)

Pseudo Instructions in gem5 are marked as nonSpeculative instructions. If I am not mistaken this only means that pseudo instructions do not execute unless older instructions have executed without fault. But, newer instructions can be executed i.e. pseudo instructions do not block the pipeline. Can

Re: [gem5-users] Pseudo Instructions (NonSpeculative)

have not > committed. > > For the detailed O3 mode, you could check out the commit source file for > more detailed implementation. > > On Fri, Apr 15, 2016 at 12:51 PM, Ayaz Akram wrote: > >> Pseudo Instructions in gem5 are marked as nonSpeculative instructions. If >&

[gem5-users] SIMD instructions on Arm

This question is not directly related to gem5, but I am asking here as a lot of community members are using gem5 for Arm simulations. I am trying to compile some SPEC2006 benchmarks for Arm without any simd instructions. I am using -mcpu=generic+nosimd flag but, when I run the benchmarks with gem5

Re: [gem5-users] SIMD instructions on Arm

-- > > *De: *"Ayaz Akram" > *À: *"gem5 users mailing list" > *Envoyé: *Samedi 30 Avril 2016 19:58:17 > *Objet: *[gem5-users] SIMD instructions on Arm > > This question is not directly related to gem5, but I am asking here as a >

Re: [gem5-users] SIMD instructions on Arm

nst when > producing your benchmark binary have been compiled using SIMD instructions. > Of course if your benchmark does not need any library then this does not > apply. > > Best, > > Arhtur. > > -- > > *De: *"Ayaz Akram" > *

[gem5-users] Branch Predictor in Minor Cpu

I have observed that branch predictor stats do not update for Minor Cpu when used with x86 (every branch predictor related stat stay 0). Changing ISA to Arm with same Minor Cpu configurations show branch predictor stats in output stats.txt file. I wonder if anyone else experienced such issue ? P.S:

Re: [gem5-users] SIMD instructions on Arm

gt;> >> When replying, please edit your Subject line so it is more specific >> than "Re: Contents of gem5-users digest..." >> >> >> Today's Topics: >> >>1. SIMD instructions on Arm (Ayaz Akram) >>2. Re: SIMD instructions on Arm

[gem5-users] Physical Address of Instructions

I wonder if there is a way to get the physical address of an instruction itself at commit stage. DynInst provides methods to get physical address of memory access but, I am not able to figure out a way to get physical address of instructions when they commit . Did someone try something similar ? (I

[gem5-users] SSE Instructions in Gem5

I am running a small C program on gem5. Disassembled binary of the program shows a lot of SSE instructions, but simulator's output stats.txt does not show any SIMD operation type committed. On generating the execution trace from gem5, I can see that those SSE instructions are decoded into operation

Re: [gem5-users] SSE Instructions in Gem5

views.gem5.org, though! We'd welcome the fixes. > > BTW, you're correct that SIMD instructions are labeled as floating point > instructions. I've noticed that too. > > Cheers, > Jason > > On Tue, Jun 21, 2016 at 3:42 PM Ayaz Akram wrote: > >> I am

Re: [gem5-users] SSE Instructions in Gem5

through these, will I be wrong in concluding that labelling of SSE micro-ops as floating point micro-ops is correct for most of the cases ? I'm not sure how close is this implementation to real x86 processors, though. On Wed, Jun 22, 2016 at 2:12 PM, Ayaz Akram wrote: > Thanks Jason. I&#

Re: [gem5-users] Syscall setitimer (#104) unimplemented

Hi, You are getting this error because your benchmark's binary contains this syscall (setitimer) which is unimplemented in gem5. Looking into syscall_emul.cc will give you a better idea. If your benchmark's functionality does not depend much on this syscall you might be able to continue simulation

[gem5-users] Operation Classes in Arm

I have a question regarding operation labeling of Arm64 instructions. I can see in reference manual [1] that most of the instructions in "floating-point and Advanced SIMD category" have both scalar and vector versions. My understanding is that source files src/arcch/arm/isa/insts/fp64.isa and src/a

Re: [gem5-users] Restoring from the checkpoint created by hack_back_ckpt.rcS

Azadeh: Regarding output JPEG file on disk image, due to COW functionality Simulation does not change the contents of disk image. So, once you are done with simulation you cannot see output files on disk image unless you turn off the COW layer. On Fri, Jul 1, 2016 at 3:09 PM, Azadeh Shirvanian <

Re: [gem5-users] Operation Classes in Arm

ed them, but didn't posted the patch yet (it is not that > difficult). > > Regards, > > -- > Fernando A. Endo, Post-doc > > INRIA Rennes-Bretagne Atlantique > France > > > 2016-06-29 16:59 GMT+02:00 Ayaz Akram : > >> I have a question regarding opera

Re: [gem5-users] Operation Classes in Arm

016-07-10 18:21 GMT+02:00 Jason Lowe-Power : > >> Or even better, post the patch on reviewboard (http://reviews.gem5.org) >> so we can incorporate your work! >> >> Cheers, >> Jason >> >> On Sat, Jul 9, 2016, 8:08 PM Ayaz Akram wrote: >> >>>

[gem5-users] Gcc 4.8.5 for Alpha

Hi All, I recently built an alpha cross compiler using crosstool-ng (version 1.22). The built cross compiler version is gcc 4.8.5 with linux kernel 3.18 headers. The problem is that the generated binaries with this cross compiler fail to run on gem5 (fault is raised saying "tried to access unmappe

Re: [gem5-users] Gcc 4.8.5 for Alpha

date kernels, latest tool > chains, Android support etc. > > Andreas > > From: gem5-users on behalf of Ayaz Akram < > aaq...@gmail.com> > Reply-To: gem5 users mailing list > Date: Tuesday, 12 July 2016 at 21:58 > To: gem5 users mailing list > Subject: [gem5-users

Re: [gem5-users] Running a Mix of two benchmarks from PARSEC

I think, the only way you can do this in FS mode is to use linux "taskset" utility and assign individual workload to a particular core. -Ayaz On Tue, Jul 12, 2016 at 9:22 PM, Hodjat Asghari-Esfeden wrote: > Hi all, > > I'm gonna make contention in L2 cache in Mesi_Two_Level cache coherency in

Re: [gem5-users] 200 ports for cache?

Following link has pretty detailed conversation on this topic: https://www.mail-archive.com/gem5-users@gem5.org/msg12864.html -- Ayaz On Thu, Jul 14, 2016 at 1:07 PM, Murat Koksal wrote: > Hello, > > In ./cpu/o3/O3CPU.py for DerivO3CPU the number of cache ports is given as > 200. Is that the

Re: [gem5-users] Gcc 4.8.5 for Alpha

upport in gcc was droped a long time ago, so > backporting it to a very recent gcc may not work. > > Regards, > > -- > Fernando A. Endo, Post-doc > > INRIA Rennes-Bretagne Atlantique > France > > > 2016-07-12 23:09 GMT+02:00 Ayaz Akram : > >> Thanks, Andreas

Re: [gem5-users] Turn off Branch Predictor for SE mode (O3 detailed CPU)

Hi ! Look at the files inside gem5/src/cpu/pred folder. These files contain implementation of branch predictors. It should not be very hard to modify the code according to your needs. Regards On Mon, Jul 25, 2016 at 1:23 AM, Zaman, Monir wrote: > Hello all, > I am trying to turn off the Branch

[gem5-users] Branch predictor and x86 minor cpu

I have observed that minor cpu for x86 does not lookup for predictions from branch prediction for control instructions. In minor cpu branch predictor is called at fetch2 stage, and I observed that for x86, in fetch2.cc file, inside the function "Fetch2::predictBranch(MinorDynInstPtr inst, BranchDat

Re: [gem5-users] modifying the operand in the 'br' instruction

Hi, I will suggest you to look at the curStaticInst (--> StaticInst) implementation and see the available functions and objects in StaticInst class that you can make use of (if you have not already done so). You can check if the ins is a control inst using "isControl()" and possibly generate the di

[gem5-users] Minor Cpu x86

I'll appreciate if someone who has used x86 minor cpu can look into output stats files of their experimental results and share if they observe the similar problem as mentioned in the following post: https://www.mail-archive.com/gem5-users@gem5.org/msg13196.html Actually based on this observation

Re: [gem5-users] Wrong opClass in x86 instructions

Hi, you can look at following patch by Fernando, to fix Arm SimdFloat ops labelling: http://reviews.gem5.org/r/3547/ This will be helpful in doing similar changes for x86. On Mon, Oct 10, 2016 at 10:19 AM, Ferran Olid wrote: > Hi all, > > I am running a code using the x86 decoder and I have

[gem5-users] gem5 Checkpoints for different ISAs

Hello ! I am trying to use gem5 pseudo instructions inside code of a benchmark to create checkpoints at certain points in program execution (after pseudo instruction is called for a specific number of times). The benchmark is compiled for both Arm and x86. Once checkpoint is created I run the benc

Re: [gem5-users] gem5 Checkpoints for different ISAs

Jason > > On Sun, Feb 12, 2017 at 1:12 PM Ayaz Akram wrote: > >> Hello ! >> >> I am trying to use gem5 pseudo instructions inside code of a benchmark to >> create checkpoints at certain points in program execution (after pseudo >> instruction is called fo

[gem5-users] x86 instructions to uops

Hi All, While playing with the x86 instructions' implementation in micro-operations, I changed the ADD_R_I implementation, such that it does not have to use limm uop and I replaced add uop with its immediate version addi. The changed code looks something like this: def macroop ADD_R_I { #limm

[gem5-users] numPhysFloatRegs in Armv8

Hi All: Referring to the following link: http://www.mail-archive.com/gem5-users@gem5.org/msg13215.html I wonder, if in the latest gem5 version, we still need to configure numPhysFloatRegs=4*num_regs (where num_regs is the number of physical fp registers to be simulated) for Armv8? Thanks for yo

Re: [gem5-users] speculative load

If you want to convert speculative instructions to non-speculative ones, you can do that by making changes in ISA related code of gem5. For example, look at nonSpec flag in src/arch/x86/isa/microops/ldstop.isa for load instructions in x86. On Tue, Jan 16, 2018 at 6:47 AM, crown wrote: > Hi >

Re: [gem5-users] gem5 to McPAT script

Check out this assignment here: http://users.ece.utexas.edu/~ljohn/teaching/382m-15/assignments/assignment4.pdf The mcpat_template.xml file you will need is also attached. On Fri, Jan 19, 2018 at 6:34 AM, JYOTIRANJAN SWAIN <516cs1...@nitrkl.ac.in> wrote: > > Hello > > please share a script to co

Re: [gem5-users] gem5 X86 Full System fails with DerivO3CPU

Hi Abhishek, I wonder if you are using the default CPU configuration for full-system or do you have any changes? Regards -Ayaz On Wed, Mar 6, 2019 at 2:20 PM Abhishek Singh < abhishek.singh199...@gmail.com> wrote: > Hello Everyone, > > I am trying to run the gem5 full system with X86 ISA and De

Re: [gem5-users] How to run gdb or debug segmentation fault in Full System O3CPU in x86 isa

Hi Abhishek, You can use gdb's remote debugger interface to debug simulated code in gem5. See details here: http://www.gem5.org/Debugging_Simulated_Code. Regards, -Ayaz On Sun, Sep 1, 2019 at 5:56 PM Abhishek Singh < abhishek.singh199...@gmail.com> wrote: > Hello Everyone, > > I am running the

Re: [gem5-users] gem5 X86 full system simulation with a recent version of ubuntu(18.04)

Hi Rubel, You can download a disk image with ubuntu 18.04 using the following link: http://dist.gem5.org/images/x86/ubuntu-18-04/base.img We have also uploaded some linux kernel binaries and associated kernel config files, which you can download from the following links: http://dist.gem5.org/ke

Re: [gem5-users] Could not specify trace_file argument in communication monitor

Hi Mohammad, As far as params are concerned, in gem5 params are passed from python to C++ objects. For example, all parameters of CommMonitor are defined in src/mem/CommMonitor.py. Once you compile gem5, you can view the generated header file for these parameters: build/X86/params/CommMonitor.hh (

Re: [gem5-users] Could not specify trace_file argument in communication monitor

am working with the latest version of gem5. > > > Thanks, > Rubel Ahmed > USF-CSE > Tampa, FL > > > On Wed, Jan 29, 2020 at 4:07 PM Ayaz Akram wrote: > >> Hi Mohammad, >> >> As far as params are concerned, in gem5 params are passed from python to

Re: [gem5-users] Thread Creation Failed Error

Hi Muhammet, If I am not mistaken configs/learning_gem5/part1/simple.py is supposed to run a simulation in system emulation (SE) mode. I don't think you will be able to run benchmarks from GAPBS without using full system (FS) simulation mode of gem5. Regards Ayaz On Mon, Feb 3, 2020 at 12:36 AM

Re: [gem5-users] Installing Shared Libraries to Image in Full Simulation

We have recently uploaded a disk image with ubuntu 18.04 installed which should have basic packages/libraries available. See the following post on the mailing list: https://www.mail-archive.com/gem5-users@gem5.org/msg17274.html You can also refer to gem5art's documentation on building your own di

Re: [gem5-users] Installing Shared Libraries to Image in Full Simulation

> Ubuntu 18.04.2 LTS gem5-host ttyS0 > > gem5-host login: root (automatic login) > > > Welcome to Ubuntu 18.04.2 LTS (GNU/Linux 4.14.134 x86_64) > > * Documentation: https://help.ubuntu.com > * Management: https://landscape.canonical.com > * Support:https://ub

Re: [gem5-users] Multiple simultaneous benchmark run on same disk image/kernel

Hi Reyad, Sharing the disk image and kernel should not be a problem. I will suggest you to make sure that the OOM (out of memory) killer is not getting activated on the system (usually logged in /var/log/messages). Regards, Ayaz On Fri, Feb 7, 2020 at 4:53 PM Hafizul Islam Reyad wrote: > > > H

Re: [gem5-users] Installing Shared Libraries to Image in Full Simulation

wanted to use this image for running multithreaded applications on x86 > O3CPU FS mode. > > > On Tue, Feb 4, 2020 at 4:12 PM Ayaz Akram wrote: > >> Hi Muhammet, >> >> This is the expected behavior. Basically, this disk image correspond to >> this tutorial

Re: [gem5-users] Multiple simultaneous benchmark run on same diskimage/kernel

ystem resource usage and never found memory usage more than 50%. > Could there be any other reason beside this? > > > > Regards, > > Reyad > > > > *From: *Ayaz Akram > *Sent: *Friday, February 7, 2020 8:19 PM > *To: *gem5 users mailing list > *Subj

Re: [gem5-users] Does KvmCPU gives timing information

Hi Abhishek, KVM cpu does not do any timing simulation and its main use is for fast forwarding. Since it uses actual hardware, you can expect near native simulation speed when compared to atomic cpu. -Ayaz On Fri, Feb 7, 2020 at 7:00 PM Abhishek Singh < abhishek.singh199...@gmail.com> wrote: >

Re: [gem5-users] Getting latency of a X86 micro-op before it is Executed or runned.

Hi Amir, Considering the execute-in-execute cpu models of gem5, I don't think it will be possible in gem5. One thing that might work for you is to generate a trace with the latency information and then use that trace later to infer the dynamic latencies of operations (this will need two gem5 runs

Re: [gem5-users] x64 support on Gem5

Hi Niranjan, Can you give some specific examples of instructions where you find these problems (and what cpu model are you using)? Is this issue on gem5 Jira ( https://gem5.atlassian.net/projects/GEM5/issues/GEM5-338?filter=allopenissues&orderby=priority%20DESC) related to branch operation type be

Re: [gem5-users] x64 support on Gem5

rmats/branch.isa > > For example, in the cpu/pred/bpred_unit.cc, when I print the following > > inst->isDirectCtrl() or inst->isIndirectCtrl() > > both flag are not set for any instruction > > Thanks > Niranjan > > > On Sat, Feb 15, 2020 at 1:56 AM Ayaz Akra

Re: [gem5-users] Changing the "inParallelMode"

Hi Yuchen, Parallel mode is currently only supported for kvm cpu model. -Ayaz > On Feb 29, 2020, at 11:25 PM, YUCHEN ZHOU wrote: > >  > Hi all, > > > > Recently I tried to parallelize the gem5's simulation engine to run on > shared-memory multicore systems. I changed the value of "inPa

Re: [gem5-users] Installing Shared Libraries to Image in Full Simulation

==> qemu: Deleting output directory... >> >> >> >> *Build 'qemu' errored: Build was halted.==> Some builds didn't complete >> successfully and had errors:--> qemu: Build was halted.* >> >> Please note I am doing ssh into the machine and

Re: [gem5-users] Changing the "inParallelMode"

rds, > > Yuchen > > > -原始邮件- > *发件人:*"Ayaz Akram" > *发送时间:*2020-03-01 15:54:03 (星期日) > *收件人:* "gem5 users mailing list" > *抄送:* m5-us...@m5sim.org > *主题:* Re: [gem5-users] Changing the "inParallelMode" > > Hi Yuchen, > &g

Re: [gem5-users] gem5 X86 full system simulation with a recent version of ubuntu(18.04)

s.py > --checkpoint-dir=/home/abs218/whisper_gem5_setup/gem5_latest/scalibility_chkpt/ > --disk-image=/home/abs218/whisper_gem5_setup/benchmarks/gem5art/base.img > --kernel=/home/abs218/new_fs/gem5/linux-4.8.13/vmlinux > --script=scalibility.rcS > > > Best regards, > > Abhishek &

[gem5-users] Re: KVM patch for FS mode and PARSEC on gem5-21

Hi Rajesh, I think the error you are seeing is because tlbs are exposed through an mmu unit in gem5 now. I guess changing line 117 in caches.py as in this file ( https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/boot-exit/configs/system/caches.py) should work for you. -A

[gem5-users] Re: gem5 Intel SGX model

Hi Jared, Not SGX, but we recently did some work on running RISC-V-based TEEs (Keystone specifically) in gem5, which you might find useful. You can look at the documentation here: https://github.com/darchr/Keystone-experiments -Ayaz On Thu, Jun 10, 2021 at 11:41 AM Jared Nye wrote: > Hello, >

[gem5-users] Re: Making an address range uncacheable RISCV FS.

Hi Deepak, RISC-V PMA is supported in gem5. You can have a look at the source here: https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/src/arch/riscv/PMAChecker.py Also, here is an example of how this can be used in the gem5 config script: https://gem5.googlesource.com/public/gem5-re

[gem5-users] Re: Fwd: Making an address range uncacheable RISCV FS.

wrote: > -- Forwarded message - > From: Deepak Mohan > Date: Wed, Jun 16, 2021 at 5:16 PM > Subject: Re: [gem5-users] Making an address range uncacheable RISCV FS. > To: Ayaz Akram > > > Hi Ayaz, > Thank you, it looks great, I was working with a previou

[gem5-users] Re: Implicit Register Dependencies in x86

Hi Mohit, I wonder if the number of Physical register file entries is becoming a bottleneck in the configuration you are using? Normally, I would expect that 'ProdLo' and 'ProdHi' registers will be renamed to some physical register and should not cause any dependency between two independent multip

[gem5-users] Re: Not able to access webpage to run_npb.py

Hi David, Please find my response to your questions below: > >1. It seems like I don’t need to do the “Setting up the environment” >since I don’t plan to create or modify npb-tests. > > I thought the npb tests are already on the disk image from “Creating a > disk image” section. > Pleas

[gem5-users] Re: Is there actual data in the DRAM?

Hi Daniel, The memory interfaces inherit from AbstractMemory, which is where the actual data is stored. I will suggest looking at src/mem/abstract_mem.cc to get a better understanding of this. -Ayaz On Mon, Dec 26, 2022 at 5:42 AM 李信德 via gem5-users wrote: > Hi everyone, > > I would like to lo

[gem5-users] Re: PerfKvmCounter::attach failed (2)

Hi Atlas, I think the host machine means the bare metal host. I have not personally run KVM CPU of gem5 on a VM, but you might find this post on the mailing list relevant: https://www.mail-archive.com/gem5-users@gem5.org/msg20996.html -Ayaz On Tue, Jan 10, 2023 at 11:16 AM Atlas Kaan Yilmaz via

[gem5-users] Re: Running OpenMP version of SPEC CPU speed 2017 benchmarks

Hi Vipin, I guess that you will have to create a new disk image by changing the benchmark build and run scripts from https://gem5.googlesource.com/public/gem5-resources/+/refs/tags/v20.1.0.5/src/spec-2017/disk-image/spec-2017/ (install-spec2017.sh and runscript.sh). You will have to add openmp re

[gem5-users] Re: Set number of register file read and write ports

Hi, Based on my understanding of O3CPU, I think your assumption is correct. However, probably parameters like issueWidth and wbWidth can be used to control maximum register read/writes indirectly. -Ayaz On Tue, Jan 17, 2023 at 3:32 AM pedro--- via gem5-users wrote: > Hi, > > I'm trying to chec

[gem5-users] Re: Running gem5 RISCV in bare-metal mode

Hi Priyanka, I think adding something like the following line in your script should solve the problem you are running into: system.platform.pci_host.pio = system.iobus.mem_side_ports -Ayaz On Tue, Jan 24, 2023 at 6:48 AM Priyanka Ankolekar via gem5-users < gem5-users@gem5.org> wrote: > Hello,

[gem5-users] Re: Limit FS memory through kernel args

Hi Joao, If you look at the source code here (in case you haven't previously): src/python/gem5/components/boards/kernel_disk_workload.py, I think the expectation is that the user-provided kernel arguments will replace the default ones. However, I agree that it might be useful to have the ability t

[gem5-users] Re: Simulation error for hello world workload

Hi Ikram, It seems like your program is using a system call (#398) which has not been tested or implemented in gem5. This can be because of a newer version of the c library or compiler. One option is to ignore this system call and see if your program still works. As a reference you can look at how

[gem5-users] Re: Accessing CPU cycles in Ruby components

Hi Ziyao, Based on my understanding, I guess for the Ruby stats that are not in Ticks, you can rely on the Ruby ClockDomain value from the configuration to convert the cycles to CPU cycles or ticks. -Ayaz On Tue, Jan 24, 2023 at 12:48 AM Ziyao Yan via gem5-users < gem5-users@gem5.org> wrote: >

[gem5-users] Re: RISCV fs mode - code won't stop running

Hi Priyanka, I am assuming you don't see any new instructions in the "trace.out" after a specific time. My understanding is that since this program is run in full system mode (bare metal), even when the program finishes the simulation loop still keeps executing (simulating the bare metal system).

[gem5-users] Re: cache line data based on memory accesses

[Copying my response from gem5 slack in case you don't see there] Hi Ghadeer, I think you should be able to dump packet data with your changes in abstract_mem.cc. access() function eventually calls getData() and writeData() of packet.hh which use getSize() which gives the size of the packet. Norm

[gem5-users] Re: gem5 always adds PCID to vaddr to lookup TLB

Hi Soramichi, We recently added the concatenation change to distinguish TLB entries of different processes to make SMT work. You can check more details here: https://gem5.atlassian.net/browse/GEM5-332 I am not sure what the behavior should be for global pages. From some discussion here: https:/

[gem5-users] Re: Interactive simulation with statistics per executable

Hi Sebastian, I use [2] as starting point but I can’t change workloads in the python > script and rerun the simulation because this would simulate another system > instead of simulating another executable in the same system. Going to python script should not simulate another system, rather once

[gem5-users] Re: gem5 always adds PCID to vaddr to lookup TLB

; decide whether it should be used. > > May I open an issue on Jira on this and assign myself? I think I have a > somewhat clear plan on how the code should be changed, but the contributing > guide says it is better to ask a developer for advise. > > Best regards, > > Soramichi &g

[gem5-users] Re: gem5 always adds PCID to vaddr to lookup TLB

Another thing to notice is that the current PCID change is intended for SE mode only (as you might have seen in the comments of the JIRA issue: https://gem5.atlassian.net/browse/GEM5-332). So, the global bit probably would not be used anyways. -Ayaz On Wed, Feb 1, 2023 at 4:14 PM Ayaz Akram

[gem5-users] Re: RISC-V FS stuck at login

Hi Joao, I will suggest looking at the last part of the following README file to understand how this disk image should be used (I think your simulation is executing an m5 exit at the boot up) : https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/develop/src/riscv-ubuntu/README.md -A

[gem5-users] Re: handle syscalls in FS (bare-metal) mode for RISCV

Hi Priyanka, If you want syscall handling you can use full-system simulation with Linux as the OS (instead of the bare metal full system). gem5 also provides a syscall emulation (SE) mode where you do not need to run any OS, and gem5 would emulate most of the system calls. -Ayaz On Wed, Feb 1, 2

[gem5-users] Re: SE Mode DMA Engine

Hi Siddharth, There is an existing CopyEngine in gem5 (src/dev/pci/copy_engine.cc) which might be similar (and helpful) to what you are trying to do. -Ayaz On Thu, Feb 2, 2023 at 2:37 AM Siddharth Sahay via gem5-users < gem5-users@gem5.org> wrote: > Hi! > What would be the best strategy for cre

[gem5-users] Re: Memory traces using CommMonitor

Hi Sadhana, I think the first number is the requestor port id (IIRC). The above trace should have all requests to the main memory as your CommMonitor is connected between the membus and MemCtrl (and all memory traffic should go through it). -Ayaz On Mon, Feb 13, 2023 at 7:52 PM Sadhana . via gem

[gem5-users] Re: Memory traces using CommMonitor

gt; 8,r,1028,4,10,476000 > 7,r,1008,4,256,525000 > 8,w,474568,4,10,574000 > > On Wed, Feb 15, 2023 at 9:12 AM Sadhana . > wrote: > >> Thank you. >> >> On Tue, Feb 14, 2023 at 4:34 PM Ayaz Akram wrote: >> >>> Hi Sadhana, >>> >>> I thin

[gem5-users] Re: Interactive simulation with statistics per executable

gt; > > *Von:* Sebastian Weber via gem5-users > *Gesendet:* Donnerstag, 2. Februar 2023 14:51 > *An:* Ayaz Akram ; The gem5 Users mailing list < > gem5-users@gem5.org> > *Cc:* Sebastian Weber > *Betreff:* [gem5-users] Re: Interactive simulation with statistics per > exec

[gem5-users] Re: Requestor ID of a Packet - How it is generated

Hi Abdlerhman, I think your understanding of different requestor IDs for a single core is correct i.e., these specify instruction and data requests. "dataRequestorId()" and "instRequestorId()" functions in src/cpu/base.hh verify this. I think prefetchers should also have their own requestor ids as

[gem5-users] Re: Questions about using gem5

Hi, Is there a way to simulate using DDR5 memory in gem5? Currently, there is no DDR5 interface in gem5. I just pushed an in-progress change here ( https://gem5-review.googlesource.com/c/public/gem5/+/68257/1/src/mem/DRAMInterface.py) to support a single channel of DDR5. This configuration still

[gem5-users] Re: Retired instructions versus ticks

Hi Priyanka, By default, the dumped stats have the total number of instructions and cycles/ticks for a specific simulation. If you want to look at these stats over smaller time intervals, one possible option is to change your gem5 run script to simulate for a specific time, dump stats, and keep re

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