Hi,
On Mon, Sep 8, 2025 at 1:37 PM John Ripple wrote:
>
> Add support for DisplayPort to the bridge, which entails the following:
> - Get and use an interrupt for HPD;
> - Properly clear all status bits in the interrupt handler;
>
> Signed-off-by: John Ripple
> ---
> V1 -> V2: Cleaned up coding
On Thu, Sep 4, 2025 at 2:14 PM Thomas Zimmermann wrote:
>
> Gma500 unnecessarily clears the framebuffer's GEM-object pointer
> before calling drm_framebuffer_cleanup(). Remove this code to make
> gma500 consistent with the rest of the drivers.
>
> The change is cosmetic, as drm_framebuffer_cleanup
On 08/09/2025 21:19, Ariel D'Alessandro wrote:
> Krzysztof,
>
> On 8/21/25 3:43 AM, Krzysztof Kozlowski wrote:
>> On Wed, Aug 20, 2025 at 02:12:51PM -0300, Ariel D'Alessandro wrote:
>>> Current, the DT bindings for MediaTek mmsys controller is missing the
>>> assigned-clocks and assigned-clocks-ra
On Tue, Sep 09, 2025 at 08:16:48AM +0200, Jens Wiklander wrote:
> On Tue, Sep 9, 2025 at 6:34 AM Sumit Garg wrote:
> >
> > On Tue, Aug 12, 2025 at 05:35:29PM -0700, Amirreza Zarrabi wrote:
> > > This patch series introduces a Trusted Execution Environment (TEE)
> > > driver for Qualcomm TEE (QTEE)
Hello Svyatoslav,
On Fri, 5 Sep 2025 19:11:06 +0300
Svyatoslav Ryhel wrote:
> пт, 5 вер. 2025 р. о 19:08 Luca Ceresoli пише:
> >
> > On Tue, 19 Aug 2025 15:16:25 +0300
> > Svyatoslav Ryhel wrote:
> >
> > > Tegra20, Tegra30 and Tegra114 have VI revision 1.
> >
> > Why? You should mention th
On Monday, 8 September 2025 12:06:01 Central European Summer Time
AngeloGioacchino Del Regno wrote:
> Il 05/09/25 12:23, Nicolas Frattaroli ha scritto:
> > The MT8196 SoC uses an embedded MCU to control frequencies and power of
> > the GPU. This controller is referred to as "GPUEB".
> >
> > It co
Add kunit tests for drm_panic.
They check that drawing the panic screen doesn't crash, but they
don't check the correctness of the resulting image.
Signed-off-by: Jocelyn Falempe
---
v2:
* Add a few checks, and more comments in the kunit tests. (Maxime Ripard).
MAINTAINERS
This adds a new drm_panic/draw_test file in debugfs.
This file allows to test the panic screen rendering at different
resolution and pixel format.
It's useful only for kernel developers that want to create or
customize a panic screen.
If you want to check the result at 1024x768 using XRGB:
cd
在 2025/9/6 01:49, Borislav Petkov 写道:
On Fri, Sep 05, 2025 at 09:24:07PM +0800, Zihuan Zhang wrote:
This patchset converts all remaining cpufreq users to rely on the
__free(put_cpufreq_policy) annotation for policy references, instead of
calling cpufreq_cpu_put() manually.
Sep 01 Zihuan Zhang
On Mon, 08 Sep 2025 10:47:25 +0200
"Danilo Krummrich" wrote:
> On Mon Sep 8, 2025 at 10:26 AM CEST, Alice Ryhl wrote:
> > On Mon, Sep 08, 2025 at 09:11:40AM +0200, Boris Brezillon wrote:
> >> Hi Alice,
> >>
> >> On Sun, 7 Sep 2025 11:39:41 +
> >> Alice Ryhl wrote:
> >>
> >> > Yeah I gu
kzalloc() already zero-initializes the destination buffers, making
strscpy() sufficient for safely copying the names. The additional
NUL-padding performed by strscpy_pad() is unnecessary.
If the destination buffer has a fixed length, strscpy() automatically
determines its size using sizeof() when
On Mon, Sep 01, 2025 at 05:03:40PM +0200, David Hildenbrand wrote:
> We can just cleanup the code by calculating the #refs earlier,
> so we can just inline what remains of record_subpages().
>
> Calculate the number of references/pages ahead of times, and record them
> only once all our tests pass
On Thu, 2025-09-04 at 09:51 -0300, Daniel Almeida wrote:
> > - gem_create_object: T::Object::ALLOC_OPS.gem_create_object,
> > - prime_handle_to_fd: T::Object::ALLOC_OPS.prime_handle_to_fd,
> > - prime_fd_to_handle: T::Object::ALLOC_OPS.prime_fd_to_handle,
> > - gem_prime
On Mon, Sep 8, 2025 at 11:16 AM Zihuan Zhang wrote:
>
>
> 在 2025/9/6 04:17, Rafael J. Wysocki 写道:
> > On Fri, Sep 5, 2025 at 3:24 PM Zihuan Zhang wrote:
> >> Replace the manual cpufreq_cpu_put() with __free(put_cpufreq_policy)
> >> annotation for policy references. This reduces the risk of refere
On 9/8/25 1:10 PM, Alex Hung wrote:
On 8/24/25 12:23, Kuan-Wei Chiu wrote:
Replace the previous O(N^2) implementation of remove_duplicates() in
with a O(N) version using a fast/slow pointer approach. The new version
keeps only the first occurrence of each element and compacts the array
in p
On Mon, Sep 08, 2025 at 07:05:17PM +0200, Michel Dänzer wrote:
> These messages are primarily intended for developers, not users
But everybody sees them! And they're flooding the console.
And most people seeing them are users, not developers.
And if those messages are only for developers, they b
On Sun, 2025-09-07 at 15:42 +0200, Christophe JAILLET wrote:
> Use devm_mutex_init() instead of hand-writing it.
>
> This saves some LoC, improves readability and saves some space in the
> generated .o file.
>
> Before:
> ==
> text data bss dec hex filename
> 36884 10296
Now that my rust skills have been honed, I noticed that there's a lot of
generics in our gem bindings that don't actually need to be here. Currently
the hierarchy of traits in our gem bindings looks like this:
* Drivers implement:
* BaseDriverObject (has the callbacks)
* DriverObject (ha
This is the first few patches that were originally part of the series to
introduce gem shmem bindings for rust into the Linux kernel, which can
be found here:
https://lkml.org/lkml/2025/8/29/1533
These patches don't have any dependencies besides needing to be applied
on top of drm-rust-next.
Lyu
Drive-by fix, it doesn't seem like anything actually uses this constant
anymore.
Signed-off-by: Lyude Paul
Reviewed-by: Danilo Krummrich
Reviewed-by: Daniel Almeida
---
rust/kernel/drm/gem/mod.rs | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/rust/kernel/drm/gem/mod.rs
On Mon, Sep 8, 2025 at 8:52 PM Lyude Paul wrote:
>
> This is the first few patches that were originally part of the series to
> introduce gem shmem bindings for rust into the Linux kernel, which can
> be found here:
>
> https://lkml.org/lkml/2025/8/29/1533
>
> These patches don't have any dependen
On 9/8/25 8:46 PM, Lyude Paul wrote:
> Just to reduce the clutter with the File<…> types in gem.rs.
>
> Signed-off-by: Lyude Paul
> Reviewed-by: Daniel Almeida
Acked-by: Danilo Krummrich
On 9/8/25 8:46 PM, Lyude Paul wrote:
> Now that my rust skills have been honed, I noticed that there's a lot of
> generics in our gem bindings that don't actually need to be here. Currently
> the hierarchy of traits in our gem bindings looks like this:
>
> * Drivers implement:
> * BaseDri
Hi,
On Sun, Sep 7, 2025 at 11:37 PM Zhongtian Wu
wrote:
>
> Add a few generic edp panels used by mt8189 chromebooks. For
> BOE-NV140WUM-N44 , the enable timing required 80ms. For
> CSW-MNE007QB3-1, the hpd_absent timing rquired 80ms, the enable timing
> required 50ms, the disable timing required
Replace kzalloc() followed by copy_from_user() with memdup_user() to
improve and simplify ta_if_load_debugfs_write() and
ta_if_invoke_debugfs_write().
No functional changes intended.
Signed-off-by: Thorsten Blum
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c | 20 ++--
1 file ch
On Mon, Sep 1, 2025 at 4:52 PM Dave Airlie wrote:
>
> On Tue, 2 Sept 2025 at 04:18, M Henning wrote:
> > Maybe we should also do this for older GPUs? eg. perhaps we should
> > also update gf100_fifo_nonstall_allow / gf100_fifo_nonstall_block ?
>
> Those actually turn off the irq at the hardware,
The pm_domain cleanup can not be devres managed as it uses struct
simplefb_par which is allocated within struct fb_info by
framebuffer_alloc(). This allocation is explicitly freed by
unregister_framebuffer() in simplefb_remove().
Devres managed cleanup runs after the device remove call and thus can
On Mon, Sep 08, 2025 at 03:04:21PM +0200, Neil Armstrong wrote:
> The QMP USB3/DP Combo PHY hosts an USB3 phy and a DP PHY on top
> of a combo glue to route either lanes to the 4 shared physical lanes.
>
> The routing of the lanes can be:
> - 2 DP + 2 USB3
> - 4 DP
> - 2 USB3
>
> Get the lanes ma
On Mon, 08 Sep 2025 15:04:17 +0200, Neil Armstrong wrote:
> The Thinkpad T14s embeds a transparent 4lanes DP->HDMI transceiver
> connected to the third QMP Combo PHY 4 lanes.
>
> The QMP USB3/DP Combo PHY hosts an USB3 phy and a DP PHY on top
> of a combo glue to route either lanes to the 4 shared
On 08.09.25 19:05, Alex Hung wrote:
>
>
> On 8/24/25 12:23, Kuan-Wei Chiu wrote:
>> Replace the custom bubble sort used for sorting reserved time
>> candidates in with the kernel's standard sort() helper. The previous
>> code had O(N^2) time complexity, while the generic kernel sort runs in
>> O(
These last two enumerated sections headings are in normal paragraphs,
making both sections merged into "Loading" section instead.
Add the headings.
Signed-off-by: Bagas Sanjaya
---
Documentation/fb/fbcon.rst | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/fb
Properly indent 8th step text (as enumerated list item) to be inline
with other steps.
Signed-off-by: Bagas Sanjaya
---
Documentation/fb/fbcon.rst | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/Documentation/fb/fbcon.rst b/Documentation/fb/fbcon.rst
index b9ddc145
Hi,
Here are reST formatting cleanup and improvements for fbcon documentation.
The shortlog below should be self-explanatory.
This series is based on docs-next tree.
Enjoy!
Bagas Sanjaya (3):
Documentation: fbcon: Add boot options and attach/detach/unload
section headings
Documentation:
Use reST syntax for admonitions (notes and custom admonition
for gotcha).
Signed-off-by: Bagas Sanjaya
---
Documentation/fb/fbcon.rst | 28
1 file changed, 16 insertions(+), 12 deletions(-)
diff --git a/Documentation/fb/fbcon.rst b/Documentation/fb/fbcon.rst
index 3
Hi Marek,
> Subject: Re: [PATCH v2 9/9] arm64: dts: imx95: Describe Mali G310
> GPU
>
> On 9/4/25 11:54 AM, Peng Fan wrote:
>
> Hello Peng,
>
> >>> @@ -1890,6 +1919,35 @@ netc_emdio: mdio@0,0 {
> >>> };
> >>> };
> >>>
> >>> + gpu_blk_ctrl: res
Hi Lyude,
On Mon, Sep 08, 2025 at 06:04:44PM -0400, Lyude Paul wrote:
> I made a very silly mistake with this commit that managed to slip by
> because I forgot to mzke sure rvkms was rebased before testing my work last
> - we can't do blanket implementations like this due to rust's orphan rule.
>
https://bugzilla.kernel.org/show_bug.cgi?id=220554
Bug ID: 220554
Summary: Display powers off after every update.
Product: Drivers
Version: 2.5
Hardware: ARM
OS: Linux
Status: NEW
Severity: normal
From: Michael Kelley Sent: Thursday, September 4, 2025 10:36 PM
>
> From: Thomas Zimmermann Sent: Thursday, September 4,
> 2025 7:56 AM
> >
> > Compositors often depend on vblanks to limit their display-update
> > rate. Without, they see vblank events ASAP, which breaks the rate-
> > limit featu
On 9/7/25 1:02 AM, Rob Clark wrote:
> On Sat, Sep 6, 2025 at 1:56 PM Akhil P Oommen
> wrote:
>>
>> On 9/3/2025 8:44 PM, Konrad Dybcio wrote:
>>> On 9/3/25 4:00 PM, Dmitry Baryshkov wrote:
On Wed, Sep 03, 2025 at 03:36:34PM +0200, Konrad Dybcio wrote:
> On 9/3/25 2:39 PM, Dmitry Baryshkov
Hi Alex,
On 9/7/2025 11:12 PM, Alexandre Courbot wrote:
> On Thu Sep 4, 2025 at 6:54 AM JST, Joel Fernandes wrote:
>> The bitfield-specific into new macro. This will be used to define
>> structs with bitfields, similar to C language.
>>
>> Signed-off-by: Joel Fernandes
>> ---
>> drivers/gpu/nova
On 08/09/2025 10:26, Akhil P Oommen wrote:
This patch series introduces the IFPC feature to the DRM-MSM driver for
Adreno GPUs. IFPC enables GMU to quickly transition GPU into a low power
state when idle and quickly resume gpu to active state upon workload
submission, hence the name 'Inter Frame
On Fri, Sep 5, 2025 at 3:24 PM Zihuan Zhang wrote:
>
> Replace the manual cpufreq_cpu_put() with __free(put_cpufreq_policy)
> annotation for policy references. This reduces the risk of reference
> counting mistakes and aligns the code with the latest kernel style.
>
> No functional change intended
On Mon, Sep 8, 2025 at 10:59 AM Ryan Eatmon wrote:
>
>
>
> On 9/8/2025 9:19 AM, Rob Clark wrote:
> > On Mon, Sep 8, 2025 at 6:39 AM Ryan Eatmon wrote:
> >>
> >>
> >>
> >> On 9/6/2025 6:24 PM, Rob Clark wrote:
> >>> On Sat, May 24, 2025 at 10:15 AM Dmitry Baryshkov
> >>> wrote:
>
> On S
Hello,
syzbot found the following issue on:
HEAD commit:76eeb9b8de98 Linux 6.17-rc5
git tree: upstream
console output: https://syzkaller.appspot.com/x/log.txt?x=1437956258
kernel config: https://syzkaller.appspot.com/x/.config?x=e0bea6c0b97a2002
dashboard link: https://syzkaller.ap
Sync from mesa commit 04e2140d8be7 ("freedreno/registers: remove python
3.9 dependency for compiling msm").
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/registers/gen_header.py | 157 +---
1 file changed, 107 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/msm/re
Synced from mesa commit 77c42c1a5752 ("freedreno/registers: Make
TPL1_BICUBIC_WEIGHTS_TABLE an array").
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 10 +-
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 10 +-
drivers/gpu/drm/msm/registers/adreno/
The upstream mesa copy of the GPU regs has shifted more things to reg64
instead of seperate 32b HI/LO reg32's. This works better with the "new-
style" c++ builders that mesa has been migrating to for a6xx+ (to better
handle register shuffling between gens), but it leaves the C builders
with missin
Now that https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37216
has synced kernel side changes back to mesa, this completes the round
trip by syncing mesa side changes back to the kernel.
Rob Clark (5):
drm/msm/registers: Remove license/etc from generated headers
drm/msm/registers: Sy
Since these generated files are no longer checked in, either in mesa or
in the linux kernel, simplify things by dropping the verbose generated
comment.
These were semi-nerf'd on the kernel side, in the name of build
reproducibility, by commit ba64c6737f86 ("drivers: gpu: drm: msm:
registers: impro
In particular, to pull in a SP_READ_SEL_LOCATION bitfield size fix to
fix a7xx GPU snapshot.
Sync from mesa commit 15ee3873aa4d ("freedreno/registers: Update GMU
register xml").
Cc: Karmjit Mahil
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 +-
drivers/gpu/d
https://bugzilla.kernel.org/show_bug.cgi?id=220553
rbmc...@gmail.com changed:
What|Removed |Added
Bisected commit-id||8345a71fc54b
Kernel Version|
Replace kmalloc_array() followed by copy_from_user() with
memdup_array_user() to improve and simplify cs_ioctl_engine_cores(),
cs_ioctl_engines(), and hl_multi_cs_wait_ioctl().
Remove the unused variable 'size_to_copy' from hl_multi_cs_wait_ioctl().
No functional changes intended.
Signed-off-by:
On 9/8/2025 2:39 PM, Miguel Ojeda wrote:
> On Mon, Sep 8, 2025 at 7:06 PM Joel Fernandes wrote:
>>
>> The issue I ran into is, without adding it to prelude, the users of register!
>> macro will have to import both bitfield! and register! macros explictly, even
>> though they're only using regis
hi Louis, thx for the nudge.
On Mon, Sep 8, 2025 at 8:38 AM Louis Chauvet
wrote:
> \
>
> Le 03/08/2025 à 05:57, Jim Cromie a écrit :
> > Describe the 3 API macros providing dynamic_debug's classmaps
> >
> > DYNDBG_CLASSMAP_DEFINE - create & export a classmap
> > DYNDBG_CLASSMAP_USE- refer to
https://bugzilla.kernel.org/show_bug.cgi?id=220553
Bug ID: 220553
Summary: Suspend to mem fails on rx5600xt (regression in
6.16.2)
Product: Drivers
Version: 2.5
Hardware: AMD
OS: Linux
Status: NE
Add support for DisplayPort to the bridge, which entails the following:
- Get and use an interrupt for HPD;
- Properly clear all status bits in the interrupt handler;
Signed-off-by: John Ripple
---
V1 -> V2: Cleaned up coding style and addressed review comments
drivers/gpu/drm/bridge/ti-sn65dsi
On 9/8/25 13:13, Dan Carpenter wrote:
On Mon, Sep 08, 2025 at 11:19:33AM -0700, Lizhi Hou wrote:
On 9/7/25 23:40, Dan Carpenter wrote:
Hello Lizhi Hou,
Commit 2f509fe6a42c ("accel/amdxdna: Add ioctl
DRM_IOCTL_AMDXDNA_GET_ARRAY") from Sep 2, 2025 (linux-next), leads to
the following (UNPUBLIS
On Mon, Sep 08, 2025 at 12:59:37PM -0500, Ryan Eatmon wrote:
>
>
> On 9/8/2025 9:19 AM, Rob Clark wrote:
> > On Mon, Sep 8, 2025 at 6:39 AM Ryan Eatmon wrote:
> > >
> > >
> > >
> > > On 9/6/2025 6:24 PM, Rob Clark wrote:
> > > > On Sat, May 24, 2025 at 10:15 AM Dmitry Baryshkov
> > > > wrote
On 9/6/25 04:36, Greg KH wrote:
> On Fri, Sep 05, 2025 at 06:09:52PM -0700, Mukesh Rathor wrote:
>> With CONFIG_HYPERV and CONFIG_HYPERV_VMBUS separated, change CONFIG_HYPERV
>> to bool from tristate. CONFIG_HYPERV now becomes the core Hyper-V
>> hypervisor support, such as hypercalls, clocks/timer
On Mon, Sep 08, 2025 at 08:39:19PM +0200, Miguel Ojeda wrote:
> On Mon, Sep 8, 2025 at 7:06 PM Joel Fernandes wrote:
> >
> > The issue I ran into is, without adding it to prelude, the users of
> > register!
> > macro will have to import both bitfield! and register! macros explictly,
> > even
> >
On Thu, 4 Sept 2025 at 21:30, Christian König wrote:
>
> On 04.09.25 04:25, Dave Airlie wrote:
> > On Wed, 3 Sept 2025 at 00:23, Christian König
> > wrote:
> >>
> >> On 02.09.25 06:06, Dave Airlie wrote:
> >>> From: Dave Airlie
> >>>
> >>> This enables all the backend code to use the list lru i
On 07/18, Melissa Wen wrote:
> On 18-07-2025 00:51, Matthew Schwartz wrote:
> [...]
>
> In short, there is a chance that you are not seeing those glitches
> because there are no changes in the pipe split when transitioning
> between 1-2 overlay planes in your hw, but the split happens on steam
> d
On Tue Sep 9, 2025 at 2:16 AM JST, Joel Fernandes wrote:
> Hi Alex,
>
> On 9/7/2025 11:12 PM, Alexandre Courbot wrote:
>> On Thu Sep 4, 2025 at 6:54 AM JST, Joel Fernandes wrote:
>>> The bitfield-specific into new macro. This will be used to define
>>> structs with bitfields, similar to C language.
On Sat, 6 Sep 2025 08:57:37 +0200 David Hildenbrand wrote:
> >> @@ -3024,6 +3025,7 @@ static int gup_fast_pud_leaf(pud_t orig, pud_t
> >> *pudp, unsigned long addr,
> >> return 0;
> >> }
> >> + pages += *nr;
> >> *nr += refs;
> >> for (; refs; re
On Tue, Aug 12, 2025 at 05:35:29PM -0700, Amirreza Zarrabi wrote:
> This patch series introduces a Trusted Execution Environment (TEE)
> driver for Qualcomm TEE (QTEE). QTEE enables Trusted Applications (TAs)
> and services to run securely. It uses an object-based interface, where
> each service is
On Mon, Sep 08, 2025 at 08:15:57AM +0200, Mike Looijmans wrote:
> Add DT binding document for TI TMDS181 and SN65DP159 HDMI retimers.
>
> The two chips have similar register maps, but different applications
> (source vs. sink).
>
> Signed-off-by: Mike Looijmans
>
> binding
This does not belong
Hi,
On 05/09/2025 00:01, Marek Vasut wrote:
> This controller can have both bridges and panels connected to it. In
> order to describe panels properly in DT, pull in dsi-controller.yaml
> and disallow only unevaluatedProperties, because the panel node is
> optional. Include example binding with pa
On 9/8/25 1:18 AM, Aleksandrs Vinarskis wrote:
> A number of existing schemas use 'leds' property to provide
> phandle-array of LED(s) to the consumer. Additionally, with the
> upcoming privacy-led support in device-tree, v4l2 subnode could be a
> LED consumer, meaning that all camera sensors shoul
Introduce common generic led consumer binding, where consumer defines
led(s) by phandle, as opposed to trigger-source binding where the
trigger source is defined in led itself.
Add already used in some schemas 'leds' parameter which expects
phandle-array. Additionally, introduce 'led-names' which
On Sun, 7 Sep 2025 11:15:20 +
Alice Ryhl wrote:
> On Sat, Sep 06, 2025 at 12:47:36AM +0200, Danilo Krummrich wrote:
> > On Fri Sep 5, 2025 at 8:18 PM CEST, Alice Ryhl wrote:
> > > On Fri, Sep 5, 2025 at 3:25 PM Boris Brezillon
> > > wrote:
> > >> On Fri, 05 Sep 2025 12:11:28 +
> > >>
A number of existing schemas use 'leds' property to provide
phandle-array of LED(s) to the consumer. Additionally, with the
upcoming privacy-led support in device-tree, v4l2 subnode could be a
LED consumer, meaning that all camera sensors should support 'leds'
and 'led-names' property via common 'v
Add a few generic edp panels used by mt8189 chromebooks. For
BOE-NV140WUM-N44 , the enable timing required 80ms. For
CSW-MNE007QB3-1, the hpd_absent timing rquired 80ms, the enable timing
required 50ms, the disable timing required 50ms. For CSW-MNE007QS3-6,
the enable timing required 50ms. For CMN-
Thanks for you review.
I have update patch v3:
https://lore.kernel.org/all/20250908063732.764289-1-wuzhongt...@huaqin.corp-partner.google.com/
On Sat, Sep 6, 2025 at 12:41 AM Doug Anderson wrote:
>
> Hi,
>
> On Fri, Sep 5, 2025 at 12:51 AM Zhongtian Wu
> wrote:
> >
> > Add a few generic edp pa
Dmitry Baryshkov 于2025年9月5日周五 22:24写道：
>
> On Fri, Sep 05, 2025 at 04:58:59PM +0800, 杨孙运 wrote:
> > HI，
> >
> > As a vendors , we have begun to attempt to contribute to the Linux,
> > and we are very willing to do so.
> > there are still many rules that we don't understand and need to learn.
>
> N
On 23. 07. 25, 21:09, Dmitry Baryshkov wrote:
On Wed, Jul 23, 2025 at 08:27:37AM +0200, Jiri Slaby (SUSE) wrote:
irq_domain_create_simple() takes fwnode as the first argument. It can be
extracted from the struct device using dev_fwnode() helper instead of
using of_node with of_fwnode_handle().
Roughly, what I am thinking (limiting it to pte+pmd case) about is the
following:
The code below looks much cleaner, that's great!
Great, I (or Aristeu if he has capacity) will clean this all up soon.
--
Cheers
David / dhildenb
From: Hans de Goede
Add 'name' argument to of_led_get() such that it can lookup LEDs in
devicetree by either name or index.
And use this modified function to add devicetree support to the generic
(non devicetree specific) [devm_]led_get() function.
This uses the standard devicetree pattern of a
This patch series introduces the IFPC feature to the DRM-MSM driver for
Adreno GPUs. IFPC enables GMU to quickly transition GPU into a low power
state when idle and quickly resume gpu to active state upon workload
submission, hence the name 'Inter Frame Power Collapse'. Since the KMD is
unaware of
On Mon, Sep 08, 2025 at 09:11:40AM +0200, Boris Brezillon wrote:
> Hi Alice,
>
> On Sun, 7 Sep 2025 11:39:41 +
> Alice Ryhl wrote:
>
> > Yeah I guess we could have unlink remove the gpuva, but then allow the
> > end-user to attach the gpuva to a list of gpuvas to kfree deferred. That
> > way
Add a new quirk to denote IFPC (Inter-Frame Power Collapse) support
for a gpu. Based on this flag send the feature ctrl hfi message to
GMU to enable IFPC support.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 5 +++--
drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 34 ++
CP_ALWAYS_ON counter falls under GX domain which is collapsed during
IFPC. So switch to GMU_ALWAYS_ON counter for any CPU reads since it is
not impacted by IFPC. Both counters are clocked by same xo clock source.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 30 ++
Since the PDC resides out of the GPU subsystem and cannot be reset in
case it enters bad state, utmost care must be taken to trigger the PDC
wake/sleep routines in the correct order.
The PDC wake sequence can be exercised only after a PDC sleep sequence.
Additionally, GMU firmware should initializ
A7XX_GEN2 generation has additional TCS slots. Poll the respective
DRV status registers before pm suspend.
Fixes: 1f8c29e80066 ("drm/msm/a6xx: Add A740 support")
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 16
1 file changed, 16 insertions(+)
diff
>From the hangcheck handler, KMD checks a few registers in GX
domain to see if the GPU made any progress. But it cannot access
those registers when IFPC is enabled. Since HW based hang detection
is pretty decent, lets rely on it instead of these registers when
IFPC is enabled.
Signed-off-by: Akhil
With IFPC, there is a probability of accessing a GX domain register when
it is collapsed, which leads to gmu fence errors. To debug this, we need
to trace every gpu register accesses and identify the one just before a
gmu fence error. So, add an ftrace to track all gpu register accesses.
Signed-of
A minor refactor to combine the subroutines for legacy a6xx GMUs under
a single check. This helps to avoid an unnecessary check and return
early from the subroutine for majority of a6xx gpus.
Also, document an intermediate unknown low power state which is not
exposed by the GMU firmware.
Signed-o
Hi Alice,
On Sun, 7 Sep 2025 11:39:41 +
Alice Ryhl wrote:
> On Sun, Sep 07, 2025 at 01:28:05PM +0200, Danilo Krummrich wrote:
> > On Sun Sep 7, 2025 at 1:15 PM CEST, Alice Ryhl wrote:
> > > On Sat, Sep 06, 2025 at 12:47:36AM +0200, Danilo Krummrich wrote:
> > >> On Fri Sep 5, 2025 at 8:1
Le 21/08/2025 à 13:25, Dmitry Baryshkov a écrit :
Default config for UML (x86_64) doesn't include any driver which
supports DRM_CLIENT_SELECTION, which makes drm_client_modeset disabled
(and correspondingly tests for that module are not executed too).
Enable DRM_VKMS and DRM_FBDEV_EMULATION i
Add the IFPC restore register list and enable IFPC support on Adreno
X1-85 gpu.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 68 ++-
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 15 +--
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1
Moving to IFPC state clears the 'Perfcounter Select' register setup
by the userspace. So, lets block the IFPC when sysprof is active by
using the perfcounter oob signal to the GMU.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 37 +++
d
Remove struct_mutex from ivb_parity_work() function.
The ivb_parity_work runs in a workqueue so it cannot race with itself.
Also, it is not protecting anything with the other remaining usage of
struct_mutex.
Signed-off-by: Luiz Otavio Mello
Suggested-by: Rodrigo Vivi
Reviewed-by: Rodrigo Vivi
This patch completes the removal of struct_mutex from the driver.
Remove the related TODO item, as the transition away from struct_mutex
is now complete.
Also clean up references to struct_mutex in i915.rst to avoid outdated
documentation.
Signed-off-by: Luiz Otavio Mello
Reviewed-by: Rodrigo V
The struct_mutex field in drm_i915_private is no longer used anywhere in
the driver. This patch removes it completely to clean up unused code and
avoid confusion.
Signed-off-by: Luiz Otavio Mello
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_driver.c | 2 --
drivers/gpu/drm/i915/i915_
Remove the use of struct_mutex from intel_guc_log.c and replace it with
a dedicated lock, guc_lock, defined within the intel_guc_log struct.
The struct_mutex was previously used to protect concurrent access and
modification of intel_guc_log->level in intel_guc_log_set_level().
However, it was
Hi
Am 18.08.25 um 13:35 schrieb Leander Kieweg:
The DRM subsystem has a set of preferred, prefixed logging functions
(drm_info, drm_warn, drm_err) which improve debuggability by including
the driver and function name in the log output.
As part of the ongoing effort to modernize logging calls,
c
On 9/8/25 2:11 PM, Boris Brezillon wrote:
> On Mon, 08 Sep 2025 13:11:32 +0200
> "Danilo Krummrich" wrote:
>> I'm saying exactly what you say: "has to be a special unlink function" ->
>> drm_gpuva_unlink_defer_put(). :)
>
> I don't see how calling drm_gpuva_unlink() instead of
> drm_gpuva_unlink_
This patch series completes the long-standing effort to eliminate usage
of the legacy struct_mutex from i915 driver.
Historically, struct_mutex was used to serialize access to global driver
state across the DRM subsystem. Over time, it has been gradually
replaced by more fine-grained and localized
The struct_mutex will be removed from the DRM subsystem, as it was a
legacy BKL that was only used by i915 driver. After review, it was
concluded that its usage was no longer necessary
This patch updates various comments in the i915/gem and i915/gt
codebase to either remove or clarify references t
On 08/09/2025 14:15, Luiz Otavio Mello wrote:
Move legacy BKL struct_mutex from drm_device to drm_i915_private, which
is the last remaining user.
Signed-off-by: Luiz Otavio Mello
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/drm_drv.c | 2 --
drivers/gpu/drm/i915/gt/uc/i
Hello Neil,
Add support for the transparent Realtek RTD2171 DP-to-HDMI bridge.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/bridge/simple-bridge.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/bridge/simple-bridge.c
b/drivers/gpu
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