On 08/09/2025 10:26, Akhil P Oommen wrote:
This patch series introduces the IFPC feature to the DRM-MSM driver for
Adreno GPUs. IFPC enables GMU to quickly transition GPU into a low power
state when idle and quickly resume gpu to active state upon workload
submission, hence the name 'Inter Frame Power Collapse'. Since the KMD is
unaware of these transitions, it must perform a handshake with the
hardware (eg: fenced_write, OOB signaling etc) before accessing registers
in the GX power domain.
Initial patches address a few existing issues that were not exposed in the
absence of IFPC. Rest of the patches are additional changes required for
IFPC. This series adds the necessary restore register list for X1-85/A750
GPUs and enables IFPC support for them.
To: Rob Clark <robin.cl...@oss.qualcomm.com>
To: Sean Paul <s...@poorly.run>
To: Konrad Dybcio <konradyb...@kernel.org>
To: Dmitry Baryshkov <lu...@kernel.org>
To: Abhinav Kumar <abhinav.ku...@linux.dev>
To: Jessica Zhang <jessica.zh...@oss.qualcomm.com>
To: Marijn Suijten <marijn.suij...@somainline.org>
To: David Airlie <airl...@gmail.com>
To: Simona Vetter <sim...@ffwll.ch>
To: Antonino Maniscalco <antomani...@gmail.com>
To: Neil Armstrong <neil.armstr...@linaro.org>
Cc: linux-arm-...@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Cc: freedr...@lists.freedesktop.org
Cc: linux-ker...@vger.kernel.org
Cc: Antonino Maniscalco <antomani...@gmail.com>
Cc: Neil Armstrong <neil.armstr...@linaro.org>
Signed-off-by: Akhil P Oommen <akhi...@oss.qualcomm.com>
---
Changes in v2:
- Elaborate commit text and add Fixes tags (Dmitry/Konrad)
- Document GMU_IDLE_STATE_RESERVED (Konrad)
- Add a memory barrier in fenced_write
- Move an error print in fenced_write to after polling
- %s/set_keepalive_vote/a6xx[gpu|preempt]_keepalive_vote (Dmitry)
- Add an "unlikely()" to read_gmu_ao_counter() (Konrad/Rob)
- Define IFPC_LONG_HYST to document a magic number
- Add a new patch to enable IFPC on A750 GPU (Neil/Antonino)
- Drop patch 12 & 17 from v1 revision
- Link to v1:
https://lore.kernel.org/r/20250720-ifpc-support-v1-0-9347aa5bc...@oss.qualcomm.com
---
Akhil P Oommen (16):
drm/msm: Update GMU register xml
drm/msm: a6xx: Fix gx_is_on check for a7x family
drm/msm/a6xx: Poll additional DRV status
drm/msm/a6xx: Fix PDC sleep sequence
drm/msm: a6xx: Refactor a6xx_sptprac_enable()
drm/msm: Add an ftrace for gpu register access
drm/msm/adreno: Add fenced regwrite support
drm/msm/a6xx: Set Keep-alive votes to block IFPC
drm/msm/a6xx: Switch to GMU AO counter
drm/msm/a6xx: Poll AHB fence status in GPU IRQ handler
drm/msm: Add support for IFPC
drm/msm/a6xx: Fix hangcheck for IFPC
drm/msm/adreno: Disable IFPC when sysprof is active
drm/msm/a6xx: Make crashstate capture IFPC safe
drm/msm/a6xx: Enable IFPC on Adreno X1-85
drm/msm/a6xx: Enable IFPC on A750 GPU
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 71 ++++++-
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 105 ++++++++--
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 14 ++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 221 ++++++++++++++++++----
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 3 +
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 10 +-
drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 34 +++-
drivers/gpu/drm/msm/adreno/a6xx_preempt.c | 40 +++-
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 +
drivers/gpu/drm/msm/msm_gpu.h | 9 +
drivers/gpu/drm/msm/msm_gpu_trace.h | 12 ++
drivers/gpu/drm/msm/msm_submitqueue.c | 4 +
drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml | 11 ++
13 files changed, 459 insertions(+), 76 deletions(-)
---
base-commit: 5cc61f86dff464a63b6a6e4758f26557fda4d494
change-id: 20241216-ifpc-support-3b80167b3532
Best regards,
Tested-by: Neil Armstrong <neil.armstr...@linaro.org> # on SM8650-HDK
Thanks,
Neil
