[PATCH v2 09/16] drm/msm/a6xx: Switch to GMU AO counter

[Akhil P Oommen]

CP_ALWAYS_ON counter falls under GX domain which is collapsed during
IFPC. So switch to GMU_ALWAYS_ON counter for any CPU reads since it is
not impacted by IFPC. Both counters are clocked by same xo clock source.

Signed-off-by: Akhil P Oommen <akhi...@oss.qualcomm.com>
---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 30 ++++++++++++++++--------------
 1 file changed, 16 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 
33a26bbd245ff49784bf1219a584936b4caa62b6..c64c84affa6821f79ea74b80b2f2014df38ec918
 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -16,6 +16,19 @@
 
 #define GPU_PAS_ID 13
 
+static u64 read_gmu_ao_counter(struct a6xx_gpu *a6xx_gpu)
+{
+       u64 count_hi, count_lo, temp;
+
+       do {
+               count_hi = gmu_read(&a6xx_gpu->gmu, 
REG_A6XX_GMU_ALWAYS_ON_COUNTER_H);
+               count_lo = gmu_read(&a6xx_gpu->gmu, 
REG_A6XX_GMU_ALWAYS_ON_COUNTER_L);
+               temp = gmu_read(&a6xx_gpu->gmu, 
REG_A6XX_GMU_ALWAYS_ON_COUNTER_H);
+       } while (unlikely(count_hi != temp));
+
+       return (count_hi << 32) | count_lo;
+}
+
 static bool fence_status_check(struct msm_gpu *gpu, u32 offset, u32 value, u32 
status, u32 mask)
 {
        /* Success if !writedropped0/1 */
@@ -376,8 +389,7 @@ static void a6xx_submit(struct msm_gpu *gpu, struct 
msm_gem_submit *submit)
        OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence)));
        OUT_RING(ring, submit->seqno);
 
-       trace_msm_gpu_submit_flush(submit,
-               gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER));
+       trace_msm_gpu_submit_flush(submit, read_gmu_ao_counter(a6xx_gpu));
 
        a6xx_flush(gpu, ring);
 }
@@ -577,8 +589,7 @@ static void a7xx_submit(struct msm_gpu *gpu, struct 
msm_gem_submit *submit)
        }
 
 
-       trace_msm_gpu_submit_flush(submit,
-               gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER));
+       trace_msm_gpu_submit_flush(submit, read_gmu_ao_counter(a6xx_gpu));
 
        a6xx_flush(gpu, ring);
 
@@ -2265,16 +2276,7 @@ static int a6xx_gmu_get_timestamp(struct msm_gpu *gpu, 
uint64_t *value)
        struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
        struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
 
-       mutex_lock(&a6xx_gpu->gmu.lock);
-
-       /* Force the GPU power on so we can read this register */
-       a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET);
-
-       *value = gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER);
-
-       a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET);
-
-       mutex_unlock(&a6xx_gpu->gmu.lock);
+       *value = read_gmu_ao_counter(a6xx_gpu);
 
        return 0;
 }

-- 
2.50.1