On Wed, 23 Apr 2025 03:12:34 +0100
Adrián Larumbe wrote:
> Add a device DebugFS file that displays a complete list of all the DRM
> GEM objects that are exposed to UM through a DRM handle.
>
> Since leaking object identifiers that might belong to a different NS is
> inadmissible, this functional
Sitronix ST7571 is a 4bit gray scale dot matrix LCD controller.
The controller has a SPI, I2C and 8bit parallel interface, this
driver is for the I2C interface only.
Reviewed-by: Thomas Zimmermann
Reviewed-by: Javier Martinez Canillas
Signed-off-by: Marcus Folkesson
---
drivers/gpu/drm/tiny/Kc
Sitronix ST7571 is a dot matrix LCD controller supporting
both 4bit grayscale and monochrome LCDs.
Reviewed-by: Conor Dooley
Reviewed-by: Javier Martinez Canillas
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Marcus Folkesson
---
.../bindings/display/sitronix,st7571.yaml | 73 +
Hi,
On 4/18/2025 5:27 PM, Jeffrey Hugo wrote:
> On 4/16/2025 4:25 AM, Maciej Falkowski wrote:
>> From: Karol Wachowski
>>
>> Introduce a heartbeat-based Timeout Detection and Recovery (TDR) mechanism.
>> The enhancement aims to improve the reliability of device hang detection by
>> monitoring hea
Hi Vivek,
Thanks for your ack.
在 2025/4/22 13:14, Kasireddy, Vivek 写道:
Hi Huan,
Subject: [PATCH 1/2] Revert "udmabuf: fix vmap_udmabuf error page set"
This reverts commit 18d7de823b7150344d242c3677e65d68c5271b04.
This given a misuse of vmap_pfn, vmap_pfn only allow none-page based
user invo
This series add support for the ST7571 LCD Controller.
It is a 4 gray scale dot matrix LCD controller that supports several
interfaces such as SPI, I2C and a 8bit parallell port.
The controlelr supports both monochrome and grayscale displays.
This driver only supports the I2C interface, but all co
From 38aa11d92f209e7529736f3e11e08dfc804bdfae Mon Sep 17 00:00:00 2001
From: Huan Yang
Date: Tue, 15 Apr 2025 10:04:18 +0800
Subject: [PATCH 1/2] Revert "udmabuf: fix vmap_udmabuf error page set"
This reverts commit 18d7de823b7150344d242c3677e65d68c5271b04.
This given a misuse of vmap_pfn, vmap
Hi Vivek
在 2025/4/22 13:22, Kasireddy, Vivek 写道:
Hi Huan,
Subject: [PATCH 2/2] udmabuf: fix vmap missed offset page
Before invoke vmap, we need offer a pages pointer array which each page
need to map in vmalloc area.
But currently vmap_udmabuf only set each folio's head page into pages,
miss
Hi,
On 23/04/2025 00:07, Jens Reidel wrote:
Hi everyone,
apologies for the mess this created. Danila's mail provider ratelimited him
halfway through sending the series and the attempt to re-try sending the second
half an hour later ended up with a new message ID (I think due to not using
--i
>From e45e4d9016262ace19db01e69d266d6218789ccd Mon Sep 17 00:00:00 2001
From: Abanoub Sameh
Date: Thu, 17 Apr 2025 23:37:21 +0200
Subject: [PATCH] Use strscpy() instead of strcpy() in
drivers/gpu/drm/drm_fb_helper.c
Use strscpy() instead of strcpy() since it is safer, and compliant with
checkpa
On 22/04/2025 15:52, Danilo Krummrich wrote:
On Tue, Apr 22, 2025 at 04:16:48PM +0200, Philipp Stanner wrote:
On Tue, 2025-04-22 at 16:08 +0200, Danilo Krummrich wrote:
On Tue, Apr 22, 2025 at 02:39:21PM +0100, Tvrtko Ursulin wrote:
Sorry I don't see the argument for the claim it is relyin
Add a helper function, xe_vm_get_property, that calls the
drm_xe_vm_get_property ioctl. Since the ioctl behaves similarly to an
xe_query in that it needs to be called once to get the size of the
return data and again to save the data, the helper function takes the
ioctl structure as a parameter.
Align with 20250403173614.67195-4-jonathan.cav...@intel.com
Add initial declarations for the xe_vm_get_property_ioctl call, including
necessary structures and IOCTL macros.
v2:
- Remove engine class and instance (Ivan)
v3:
- Add declares for fault type, access type, and fault level (Matt Brost,
Add tests to xe_vm that exercise the new DRM_IOCTL_XE_VM_GET_PROPERTY
ioctl. Specifically, add input validation tests that exercise the
return values for improperly formatted ioctl structures.
v2:
- Make vm creation consistent between patches (jcavitt)
Signed-off-by: Jonathan Cavitt
---
tests/
Add a test to xe_vm that determines if pagefaults are correctly tracked
and reported by the DRM_IOCTL_XE_VM_GET_PROPERTY.
v2:
- s/pageproperty/pagefaults
Signed-off-by: Jonathan Cavitt
Suggested-by: Jianxun Zhang
Suggested-by: Stuart Summers
---
tests/intel/xe_vm.c | 156 +
Add tests that exercise the new drm_xe_vm_get_property uapi,
specifically for ioctl input validation and for determining that
pagefaults are correctly tracked and returned by the reporter.
v2:
- Remove engine class and instance (Ivan)
v3:
- Add declares for fault type, access type, and fault leve
From: Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and replace
DPU_DATA_HCTL_EN feature bit with the core_major_ver >= 5 check.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +--
drivers/gpu/drm/msm/d
From: Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and replace
DPU_CTL_ACTIVE_CFG feature bit with the core_major_ver >= 5 check.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 8 ++--
drive
From: Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and replace
DPU_INTF_INPUT_CTRL feature bit with the core_major_ver >= 5 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 4
drivers/gpu/drm/msm/disp/dpu1/cata
Some time ago we started the process of converting HW blocks to use
revision-based checks instead of having feature bits (which are easy to
miss or to set incorrectly). Then the process of such a conversion was
postponed. (Mostly) finish the conversion. The only blocks which still
have feature bits
From: Dmitry Baryshkov
Stop declaring DPU_DSPP_PCC as a part of the DSPP features, use the
presence of the PCC sblk to check whether PCC is present in the hardware
or not.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 4
drivers/gpu/drm/msm
From: Dmitry Baryshkov
Inline the _setup_dspp_ops() function, it makes it easier to handle
different conditions involving DSPP configuration.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff -
From: Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and replace
DPU_CTL_FETCH_ACTIVE feature bit with the core_major_ver >= 7 check.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +--
drivers/gpu/drm/m
From: Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and replace
DPU_PINGPONG_DSC feature bit with the core_major_ver < 7 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h | 2 --
drivers/gpu/drm/msm/disp/dpu1/catalog/dp
From: Dmitry Baryshkov
The INTF_SC7280_MASK is equal to the INTF_SC7180_MASK. Stop defining a
separate symbol and use the INTF_SC7180_MASK instead.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h| 8
drivers/gpu/
From: Dmitry Baryshkov
Inline the _setup_dsc_ops() function, it makes it easier to handle
different conditions involving DSC configuration.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 17 ++---
1 file changed, 6 insertions(+), 11 deletions(-)
d
From: Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and replace
DPU_MDP_AUDIO_SELECT feature bit with the core_major_ver == 8 ||
core_major_ver == 5 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 1 -
drivers/gpu/drm
From: Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and replace
DPU_PINGPONG_DITHER feature bit with the core_major_ver >= 3 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 10 --
drivers/gpu/drm/msm/disp/dpu
From: Dmitry Baryshkov
Drop unused LM features from the current codebase.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
b/drivers/gpu
From: Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and replace
DPU_MDP_VSYNC_SEL feature bit with the core_major_ver < 5 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu
From: Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and drop the
DPU_DIM_LAYER feature bit. It is currently unused, but can be replaed
with the core_major_ver >= 4 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 3 ---
On 2/26/2025 6:25 PM, Dmitry Baryshkov wrote:
The LVDS/LCDC controller uses pixel clock coming from the multimedia
controller (mmcc) rather than using the PLL directly. Stop using LVDS
PLL directly and register it as a clock provider. Use lcdc_clk as a
pixel clock for the LCDC.
Reviewed-by: K
sysmembar is a critical operation that the GSP falcon needs to perform
in the reset sequence. Add some code comments to clarify.
Signed-off-by: Joel Fernandes
---
drivers/gpu/nova-core/gpu.rs | 11 ++-
drivers/gpu/nova-core/regs.rs | 2 ++
2 files changed, 12 insertions(+), 1 deletion(
As reported by Andy, the Kernel build system runs kernel-doc script for DRM,
when W=1. Due to Python's normal behavior, its JIT compiler will create
a bytecode and store it under scripts/lib/*/__pycache__. As one may be using
O= and even having the sources on a read-only mount point, disable its
c
As reported by Andy, kernel-doc.py is creating a __pycache__
directory at build time.
Disable creation of __pycache__ for the libraries used by
kernel-doc.py, when excecuted via the build system or via
scripts/find-unused-docs.sh.
Reported-by: Andy Shevchenko
Closes: https://lore.kernel.org/linu
Sitronix ST7571 is a 4bit gray scale dot matrix LCD controller.
The controller has a SPI, I2C and 8bit parallel interface, this
driver is for the I2C interface only.
Reviewed-by: Thomas Zimmermann
Reviewed-by: Javier Martinez Canillas
Signed-off-by: Marcus Folkesson
---
drivers/gpu/drm/tiny/Kc
Sitronix ST7571 is a dot matrix LCD controller supporting
both 4bit grayscale and monochrome LCDs.
Reviewed-by: Conor Dooley
Reviewed-by: Javier Martinez Canillas
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Marcus Folkesson
---
.../bindings/display/sitronix,st7571.yaml | 73 +
Add MAINTAINERS entry for the Sitronix ST7571 dot matrix LCD
controller.
Reviewed-by: Thomas Zimmermann
Reviewed-by: Javier Martinez Canillas
Signed-off-by: Marcus Folkesson
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index
251b1f3d0e922
Marcus Folkesson writes:
> This series add support for the ST7571 LCD Controller.
> It is a 4 gray scale dot matrix LCD controller that supports several
> interfaces such as SPI, I2C and a 8bit parallell port.
> The controlelr supports both monochrome and grayscale displays.
>
> This driver only
From: Dmitry Baryshkov
Only SSPP, WB and VBIF still have feature bits remaining, all other
hardware blocks don't have feature bits anymore. Remove the 'features'
from the DPU_HW_BLK_INFO so that it doesn't get included into hw info
structures by default and only include it when necessary.
Signed
From: Dmitry Baryshkov
Drop unused MDP TOP features from the current codebase.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 13 -
1 file changed, 13 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
b/drivers/gpu/drm/
From: Dmitry Baryshkov
Inline the _setup_ctl_ops() function, it makes it easier to handle
different conditions involving CTL configuration.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 98 ++
1 file changed, 47 insertions(+), 51 d
From: Dmitry Baryshkov
Continue cleanup of the feature flags and replace the last remaining LM
feature with a bitfield flag, simplifying corresponding data structures
and access.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 8
drivers
From: Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and replace
DPU_CTL_VM_CFG feature bit with the core_major_ver >= 7 check.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 8 ++--
drivers/
Continue migration to the MDSS-revision based checks and replace
DPU_WB_INPUT_CTRL feature bit with the core_major_ver >= 5 check.
Signed-off-by: Dmitry Baryshkov
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/c
From: Dmitry Baryshkov
Inline the _setup_mixer_ops() function, it makes it easier to handle
different conditions involving LM configuration.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 24 +---
1 file changed, 9 insertions(+), 15 deletion
On April 24, 2025, 1:18 a.m. UTC
Alexandre Courbot wrote:
> Since this just renames fields, would you be ok if I squashed this one
> into the relevant patch of my series, alongside a
>
> [joelagn...@nvidia.com: give better names to FalconAppifHdrV1's fields]
>
> ?
Yes, sounds good to me. Thanks
Add check for the return value of alloc_ordered_workqueue()
in xe_gt_alloc() to catch potential exception.
Fixes: e2d84e5b2205 ("drm/xe: Mark GT work queue with WQ_MEM_RECLAIM")
Cc: sta...@vger.kernel.org
Signed-off-by: Haoxiang Li
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/xe/xe_gt.c | 2
From: Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and replace
DPU_MDP_PERIPH_0_REMOVED feature bit with the core_major_ver >= 8 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/cat
From: Dmitry Baryshkov
Continue cleanup of the feature flags and replace the last remaining CTL
feature with a bitfield flag, simplifying corresponding data structures
and access.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 6 +++---
drivers/
[Why]
Notice few problems under I2C-write-over-Aux with
Write_Status_Update_Request flag set cases:
- I2C-write-over-Aux request with
Write_Status_Update_Request flag set won't get sent
upon the reply of I2C_ACK|AUX_ACK followed by “M”
Value. Now just set the flag but won't send out
- The I
These two patches are trying to fix how we handle I2C-Over_AUX
transactions when sink side can only complte partial data at one time.
We encounter EDID reading error with specific monitor and cause mode
list can only be lower resolutions. After analysis, the monitor will
reply I2C_ACK|AUX_ACK foll
[Why]
There is no handling for I2C-read-over-AUX when receive reply of
I2C_ACK|AUX_ACK followed by the total number of data bytes Fewer
than LEN + 1
[How]
Refer to DP v2.1: 2.11.7.1.6.3 & 2.11.7.1.6.4, repeat the identical
I2C-read-over-AUX transaction with the updated LEN value equal to
the origi
The memory allocated by msm_fence_alloc() actually is the
container of msm_fence_alloc()'s return value. Thus, just
free its return value is not enough.
Add a helper 'msm_fence_free()' in msm_fence.h/msm_fence.c
to do the complete job.
Fixes: f94e6a51e17c ("drm/msm: Pre-allocate hw_fence")
Cc: sta
From: Dmitry Baryshkov
The MSM DisplayPort driver implements several HDMI codec functions
in the driver, e.g. it manually manages HDMI codec device registration,
returning ELD and plugged_cb support. In order to reduce code
duplication reuse drm_hdmi_audio_* helpers and drm_bridge_connector
integ
:
- Rebase on drm-misc/drm-next
- Silent checkpatch --strict warnings
- Link to v5:
https://lore.kernel.org/r/20250423-st7571-v5-0-a283b752a...@gmail.com
Changes in v5:
- Use bitfield macros where appropriate
- Add comments where needed
- Link to v4:
https://lore.kernel.org/r/20250415-st7571-v4-0
From: Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and replace
DPU_CTL_DSPP_SUB_BLOCK_FLUSH feature bit with the core_major_ver >= 7
check.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +--
drivers/g
From: Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and replace
DPU_INTF_STATUS_SUPPORTED feature bit with the core_major_ver >= 5
check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cat
From: Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and replace
DPU_DSC_HW_REV_1_2 feature bit with the core_major_ver >= 7 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 10 --
drivers/gpu/drm/msm/disp/dpu1
From: Dmitry Baryshkov
The DPU_PINGPONG_TE2 is unused by the current code (and can further be
replaced by the checking for the te2 sblk presense). Other feature bits
are completely unused. Drop them from the current codebase.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/ca
From: Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and replace
DPU_SSPP_QOS_8LVL feature bit with the core_major_ver >= 4 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 +++---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.
From: Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and replace
DPU_DSC_OUTPUT_CTRL feature bit with the core_major_ver >= 5 check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 4
drivers/gpu/drm/msm/disp/dpu1/catalo
From: Dave Airlie
In order for modular GPU memory mgmt TTM to adjust the GPU
statistic we need to export the stat change functionality.
Signed-off-by: Dave Airlie
---
mm/memcontrol.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/mm/memcontrol.c b/mm/memcontrol.c
index 25471a0fd0be..68b23
From: Dave Airlie
Doing proper integration of TTM system memory allocations with
memcg is a difficult ask, primarily due to difficulties around
accounting for evictions properly.
However there are systems where userspace will be allocating
objects in system memory and they won't be prone to migr
From: Dave Airlie
This adds the memcg object for any user allocated object,
and adds account_op to necessary paths which might populate
a tt object.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 7 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c| 2 ++
drive
From: Dave Airlie
Discrete and Integrated GPUs can use system RAM instead of
VRAM for all or some allocations. These allocations happen
via drm/ttm subsystem and are currently not accounted for
in cgroups.
Add a gpu statistic to allow a place to visualise allocations
once they are supported.
Si
Hey,
I've been tasked to look into this, and I'm going start from hopeless
naivety and see how far I can get. This is an initial attempt to hook
TTM system memory allocations into memcg and account for them.
It does:
1. Adds memcg GPU statistic,
2. Adds TTM memcg pointer for drivers to set on the
From: Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and replace
DPU_CTL_HAS_LAYER_EXT4 feature bit with the core_major_ver >= 9 check.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 12 ++---
On Mon, Apr 07, 2025 at 08:29:11AM +0100, Matthew Auld wrote:
> On 04/04/2025 18:02, Matthew Brost wrote:
> > On Fri, Apr 04, 2025 at 09:19:34AM +0100, Matthew Auld wrote:
> > > On 03/04/2025 22:25, Matthew Brost wrote:
> > > > On Fri, Mar 28, 2025 at 06:10:36PM +, Matthew Auld wrote:
> > > > >
On 17/04/2025 00:04, Vignesh Raman wrote:
Add jobs to run dt_binding_check and dtbs_check. If warnings are seen,
exit with a non-zero error code while configuring them as warning in
the GitLab CI pipeline.
Signed-off-by: Vignesh Raman
Reviewed-by: Maxime Ripard
Acked-by: Dmitry Baryshkov
-
Hi Vignesh,
Thanks for this version, please see my comments below.
On 17/04/2025 00:04, Vignesh Raman wrote:
Add jobs to validate devicetrees and run KUnit tests.
Pipeline link,
https://gitlab.freedesktop.org/vigneshraman/linux/-/pipelines/1407489
I see this message:
WARNING: Running pip as
On Wed, Apr 23, 2025 at 10:16:32PM +0200, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> It turns out that there are no platforms that have PCI but don't have an MMU,
> so adding a Kconfig dependency on CONFIG_PCI simplifies build testing kernels
> for those platforms a lot, and avoids a lot of i
On Mon, Apr 21, 2025 at 10:18:24PM +0200, Barnabás Czémán wrote:
> From: Daniil Titov
>
> Modify existing MSM8917 driver to support MSM8937 SoC. Override frequencies
> which are different in this chip. Register all the clocks to the framework
> for the clients to be able to request for them. Add
This is v11 of the MT8186 Chromebook device tree series.
---
Changes in v11:
- PATCH 1/2: Remove redundant items.
- Link to
v10:https://lore.kernel.org/all/20250423093647.4074135-2-cengjian...@huaqin.corp-partner.google.com/
Changes in v10:
- PATCH 1/2: Add enum for ponyta sku.
- Link to
v9:http
Thanks a lot for doing this, this was severely missing from the
WPR2 patchset.
Due to the strong focus on documentation, and in order to ease merging,
I think it makes sense to keep this separate from the WPR2 patchset and
merge it on top of it. Danilo, would that work for you?
On Thu Apr 24, 202
Hi Andy,
On Tue, 22 Apr 2025 10:57:33 +0300, Andy Shevchenko wrote:
> On Mon, Apr 21, 2025 at 10:35:29AM -0600, Jonathan Corbet wrote:
>> Dmitry Baryshkov writes:
[...]
>> > Would it be possible to properly support O= and create pyc / pycache
>> > inside the object/output dir?
>>
>> I have to c
On 4/17/2025 4:14 PM, Dmitry Baryshkov wrote:
> On Thu, Apr 17, 2025 at 11:09:08AM +0530, Ayushi Makhija wrote:
>> From: Ayushi Makhija
>>
>> In the anx7625_sink_detect(), the device is checked to see
>> if it is a panel bridge, and it always sends a "connected"
>> status to the connector. When ad
This is v10 of the MT8186 Chromebook device tree series.
---
Changes in v10:
- PATCH 1/2: Add enum for ponyta sku.
- Link to
v9:https://lore.kernel.org/all/20250328094034.3400233-2-cengjian...@huaqin.corp-partner.google.com/
Changes in v9:
- PATCH 2/2: Add sound model to fix the warning.
- Link t
Ponyta is a custom label Chromebook based on MT8186. It is a
self-developed project of Huaqin and has no fixed OEM.
Signed-off-by: Jianeng Ceng
---
Changes in v10:
- PATCH 1/2: Add enum for ponyta sku.
- Link to
v9:https://lore.kernel.org/all/20250328094034.3400233-2-cengjian...@huaqin.corp-part
MT8186 ponyta, known as huaqin custom label, is a
MT8186 based laptop. It is based on the "corsola" design.
It includes LTE, touchpad combinations.
Reviewed-by: AngeloGioacchino Del Regno
Signed-off-by: Jianeng Ceng
---
Changes in v10:
- No change.
Changes in v9:
- PATCH 2/2: Add sound model t
On 18/04/2025 13:25, Boris Brezillon wrote:
> Tile-based GPUs come with a set of constraints that are not present
> when immediate rendering is used. This new document tries to explain
> the differences between tile/immediate rendering, the problems that
> come with tilers, and how we plan to addre
Minimum HBlank is programmed to address jitter for high resolutions with
high refresh rates that have small Hblank, specifically where Hblank is
smaller than one MTP.
TODO: Add the min_hblank calculation for hdmi as well.
v2: move from intel_audio.c to intel_dp.c
some correction in link_bpp_x
Signed-off-by: Arun R Murthy
---
Changes in v5:
- EDITME: describe what is new in this series revision.
- EDITME: use bulletpoints and terse descriptions.
- Link to v4:
https://lore.kernel.org/r/20250422-hblank-v4-0-bdb7bd9c4...@intel.com
Changes in v3:
- EDITME: describe what is new in this ser
Unify the function to calculate the link symbol cycles for both dsc and
non-dsc case and export the function so that it can be used in the
respective platform display drivers for other calculations.
v2: unify the fn for both dsc and non-dsc case (Imre)
v3: rename drm_dp_link_symbol_cycles to drm_d
On 23/04/2025 09:48, Danilo Krummrich wrote:
On Wed, Apr 23, 2025 at 08:34:08AM +0100, Tvrtko Ursulin wrote:
IMO it is better to leave it. Regardless of whether it was added because
some driver is actually operating like that, it does describe a _currently_
workable option to avoid memory lea
On Tue Apr 22, 2025 at 8:45 PM JST, Danilo Krummrich wrote:
> On Sun, Apr 20, 2025 at 09:19:41PM +0900, Alexandre Courbot wrote:
>> A page of system memory is reserved so sysmembar can perform a read on
>> it if a system write occurred since the last flush. Do this early as it
>> can be required to
On Tue, Apr 15, 2025 at 02:19:00PM +0200, Philipp Stanner wrote:
> Nouveau is mostly designed in a way that it's expected that fences only
> ever get signaled through nouveau_fence_signal(). However, in at least
> one other place, nouveau_fence_done(), can signal fences, too. If that
> happens (rac
Hi Sumit,
On Wed, Apr 23, 2025 at 08:53:20PM +0530, Sumit Semwal wrote:
> Hello Jared,
>
> On Wed, 23 Apr 2025 at 00:49, Jared Kangas wrote:
> >
> > Hi all,
> >
> > This patch series is based on a previous discussion around CMA heap
> > naming. [1] The heap's name depends on the device name, whi
On Tue, Apr 22, 2025 at 10:04:11AM -0700, Matthew Brost wrote:
> From: Himal Prasad Ghimiray
>
> This commit adds a new flag, devmem_only, to the drm_gpusvm structure. The
> purpose of this flag is to ensure that the get_pages function allocates
> memory exclusively from the device's memory. If t
On Wed, 23 Apr 2025 at 09:55, Akhil P Oommen wrote:
>
> On 4/23/2025 5:27 AM, Konrad Dybcio wrote:
> > On 4/21/25 10:13 PM, Rob Clark wrote:
> >> On Fri, Apr 18, 2025 at 9:00 AM Akhil P Oommen
> >> wrote:
> >>>
> >>> On 4/18/2025 6:40 AM, Connor Abbott wrote:
> On Thu, Apr 17, 2025, 1:50 PM
On Wed, Apr 23, 2025 at 06:23:33PM +0530, Arun R Murthy wrote:
> Unify the function to calculate the link symbol cycles for both dsc and
> non-dsc case and export the function so that it can be used in the
> respective platform display drivers for other calculations.
>
> v2: unify the fn for both
On 22/04/2025 23:31, Danila Tikhonov wrote:
This panel is used in Google Pixel 4a (google,sunfish). Document the
corresponding string.
Signed-off-by: Danila Tikhonov
---
.../bindings/display/panel/samsung,ams581vf01.yaml| 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
di
On 22/04/2025 23:20, Nathan Chancellor wrote:
Clang warns (or errors with CONFIG_WERROR=y):
drivers/gpu/drm/panel/panel-himax-hx8279.c:838:6: error: variable
'goa_even_valid' is used uninitialized whenever 'if' condition is false
[-Werror,-Wsometimes-uninitialized]
838 | if (nu
On Tue, Apr 22, 2025 at 4:01 PM Alexei Starovoitov
wrote:
>
> On Tue, Apr 22, 2025 at 12:57 PM T.J. Mercier wrote:
> >
> > On Mon, Apr 21, 2025 at 4:39 PM Alexei Starovoitov
> > wrote:
> > >
> > > On Mon, Apr 21, 2025 at 1:40 PM T.J. Mercier wrote:
> > > >
> > > > > > new file mode 100644
> > >
On Wed, Apr 23, 2025 at 06:32:07PM +0200, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> goa_even_valid is only initialized in one branch but not the other:
>
> drivers/gpu/drm/panel/panel-himax-hx8279.c:838:6: error: variable
> 'goa_even_valid' is used uninitialized whenever 'if' condition is
On Wed, Apr 23, 2025 at 11:10:51AM +0100, Tvrtko Ursulin wrote:
>
> On 23/04/2025 09:48, Danilo Krummrich wrote:
> > On Wed, Apr 23, 2025 at 08:34:08AM +0100, Tvrtko Ursulin wrote:
> > >
> > > IMO it is better to leave it. Regardless of whether it was added because
> > > some driver is actually o
On 4/22/25 11:31 PM, Danila Tikhonov wrote:
> Add base dtsi for SM7150-AA/SM7150-AB/SM7150-AC SoCs
>
> Co-developed-by: David Wronek
> Signed-off-by: David Wronek
> Co-developed-by: Jens Reidel
> Signed-off-by: Jens Reidel
> Signed-off-by: Danila Tikhonov
> ---
[...]
> + cpu0: c
On 4/23/25 4:56 PM, Rob Clark wrote:
> On Tue, Apr 22, 2025 at 11:55 PM Akhil P Oommen
> wrote:
>>
>> On 4/23/2025 5:27 AM, Konrad Dybcio wrote:
>>> On 4/21/25 10:13 PM, Rob Clark wrote:
On Fri, Apr 18, 2025 at 9:00 AM Akhil P Oommen
wrote:
>
> On 4/18/2025 6:40 AM, Connor Abbo
6.12-stable review patch. If anyone has any objections, please let me know.
--
From: Thomas Zimmermann
commit 76c332d119f9048c6e16b52359f401510f18b2ff upstream.
Fix an off-by-one error when setting the vblanking start in
. Commit d6460bd52c27 ("drm/mgag200: Add dedicated
varia
On Tue, Apr 8, 2025 at 9:42 AM Bartosz Golaszewski wrote:
>
> From: Bartosz Golaszewski
>
> struct gpio_chip now has callbacks for setting line values that return
> an integer, allowing to indicate failures. Convert the driver to using
> them.
>
> Signed-off-by: Bartosz Golaszewski
> ---
> Commi
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