On 4/22/25 11:31 PM, Danila Tikhonov wrote:
> Add base dtsi for SM7150-AA/SM7150-AB/SM7150-AC SoCs
>
> Co-developed-by: David Wronek <da...@mainlining.org>
> Signed-off-by: David Wronek <da...@mainlining.org>
> Co-developed-by: Jens Reidel <adr...@mainlining.org>
> Signed-off-by: Jens Reidel <adr...@mainlining.org>
> Signed-off-by: Danila Tikhonov <dan...@jiaxyga.com>
> ---
[...]
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "qcom,kryo470";
Please split this into Kryo 470 silver and gold, with the former being
based on CA55 and the latter on CA76
[...]
> + pmu-a55 {
> + compatible = "arm,cortex-a55-pmu";
> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
> + };
> +
> + pmu-a76 {
> + compatible = "arm,cortex-a78-pmu";
> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
> + };
Please update this, mimicking
2c06e0797c32 ("arm64: dts: qcom: sm8650: add PPI interrupt partitions for the
ARM PMUs")
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> +
> + cpu_pd0: power-domain-cpu0 {
> + #power-domain-cells = <0>;
> + power-domains = <&cluster_pd>;
> + domain-idle-states = <&little_cpu_sleep_0
> + &little_cpu_sleep_1>;
<&foo>,
<&foo2>;
because they are phandles to separate things - DTC treats them equally
though..
[...]
> + interconnects = <&aggre1_noc MASTER_QUP_0
> QCOM_ICC_TAG_ALWAYS
> + &config_noc SLAVE_QUP_0
> QCOM_ICC_TAG_ALWAYS>,
> + <&gem_noc MASTER_AMPSS_M0
> QCOM_ICC_TAG_ALWAYS
> + &config_noc SLAVE_QUP_0
> QCOM_ICC_TAG_ALWAYS>,
Paths involving AMPSS_M0 (the cpu endpoint) should be ACTIVE_ONLY,
this applies to the entire file and all paths
[...]
> + remoteproc_adsp: remoteproc@62400000 {
> + compatible = "qcom,sm7150-adsp-pas";
> + reg = <0x0 0x62400000 0x0 0x100>;
This region is 0x10_000 long
[...]
> + adreno_smmu: iommu@5040000 {
> + compatible = "qcom,sm7150-smmu-v2",
> + "qcom,adreno-smmu",
> + "qcom,smmu-v2";
> + reg = <0x0 0x05040000 0x0 0x10000>;
> +
> + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
> +
> + clocks = <&gpucc GPU_CC_AHB_CLK>,
> + <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
> + clock-names = "ahb",
> + "bus",
> + "iface";
> +
> + power-domains = <&gpucc CX_GDSC>;
> +
> + #iommu-cells = <1>;
> + #global-interrupts = <2>;
Add `dma-coherent` and check whether the GPU still works
[...]
> + };
> +
> + gmu: gmu@506a000 {
> + compatible = "qcom,adreno-gmu-618.0",
> + "qcom,adreno-gmu";
> + reg = <0x0 0x0506a000 0x0 0x31000>,
Make it 0x26_000 so that it doesn't leak into GPU_CC
[...]
> + tsens0: thermal-sensor@c263000 {
> + compatible = "qcom,sm7150-tsens",
> + "qcom,tsens-v2";
> + reg = <0x0 0x0c263000 0x0 0x1ff>, /* TM */
> + <0x0 0x0c222000 0x0 0x1ff>; /* SROT */
Please remove these comments
[...]
> + intc: interrupt-controller@17a00000 {
> + compatible = "arm,gic-v3";
> + reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
> + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
And these ones too
[...]
> + thermal-zones {
Please adjust this against
https://lore.kernel.org/linux-arm-msm/20250219-x1e80100-thermal-fixes-v1-0-d110e44ac...@linaro.org/
(keep only critical trips with no sw cooling for the CPU, etc.)
Konrad
