> -Original Message-
> From: Laszlo Ersek
> Sent: Monday, July 13, 2020 9:02 PM
> To: devel@edk2.groups.io; af...@apple.com; Wasim Khan
>
> Cc: Mike Kinney ; liming@intel.com; Leif
> Lindholm (Nuvia address)
> Subject: Re: [edk2-devel] [edk2-discuss] Need
Hello
Any comments ?
> -Original Message-
> From: Wasim Khan
> Sent: Friday, July 10, 2020 6:20 PM
> To: michael.d.kin...@intel.com; liming@intel.com; devel@edk2.groups.io
> Subject: [edk2-discuss] Need memory barriers in IoLib for AARCH64
>
> Hello
Hello,
MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf:
IoLib library uses IoLibArm.c for AARCH64/ARM architecture and IoLib.c for
other architectures.
While IoLib.c already has memory barriers in MmioWrite functions, there
barriers are missing in IoLibArm.c
Is there any reason for **
From: Wasim Khan
Enable PlatformDxe driver for LX2160aRdbPkg
Signed-off-by: Wasim Khan
Reviewed-by: Leif Lindholm
---
Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc | 2 ++
Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf | 3 +++
2 files changed, 5 insertions(+)
diff --git a/Platform/NXP
From: Wasim Khan
Enable NetworkPkg for LX2160aRdbPkg Platform to
enable networking stack and test PCIe ethernet NIC.
Signed-off-by: Wasim Khan
---
Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc | 11 +++
Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf | 5 +
2 files changed, 16
From: Wasim Khan
PCIe Layerscape controller in LX2160A-Rev2 is not completely
ECAM-compliant. It is non-ECAM only for the root bus (bus 0)
and for any other bus underneath the root bus it does support
ECAM access.
One approach can be to setup the controller in firmware and
expose bus[0x1-0xff
From: Wasim Khan
Define PCIe related PCDs for LX2160A.
Signed-off-by: Wasim Khan
Reviewed-by: Leif Lindholm
---
Silicon/NXP/LX2160A/LX2160A.dsc.inc | 5 +
1 file changed, 5 insertions(+)
diff --git a/Silicon/NXP/LX2160A/LX2160A.dsc.inc
b/Silicon/NXP/LX2160A/LX2160A.dsc.inc
index
From: Wasim Khan
Enable generic PCIe drivers and Wire up PciHostBridgeLib,
PciSegmentLib and PciCpuIo2Dxe.
Signed-off-by: Wasim Khan
Reviewed-by: Leif Lindholm
---
Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc | 9 +
Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf | 7 +++
2 files
From: Wasim Khan
Add PlatformDxe to do platform specific work.
At present it sets PCDs for PCIe controller based on
SoC version, which are used later during initialization
of PCIe controller.
Signed-off-by: Wasim Khan
---
Platform/NXP/LX2160aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf | 35
From: Wasim Khan
LX2160-Rev1 and LX2160-Rev2 has different PCIe controller.
This patch series adds PCIe support for LX2160aRdbPkg which includes
- Add PCIe space in VirtualMemoryMap
- Platform driver to check SoC version and sets PCDs for PCIe controller, which
are used by PciHostBridgeLib and
From: Wasim Khan
LX2160A SoC has 6 PCIe controllers with 32GB space available
for each controller. A platform may have different PCIe controllers
enabled based on the RCW used to boot platform.
Add space for all PCIe controllers in VirtualMemoryMap.
Signed-off-by: Wasim Khan
---
Platform/NXP
> -Original Message-
> From: Leif Lindholm
> Sent: Thursday, June 18, 2020 3:22 PM
> To: Wasim Khan (OSS)
> Cc: devel@edk2.groups.io; Meenakshi Aggarwal
> ; Varun Sethi ;
> ard.biesheu...@arm.com; Wasim Khan
> Subject: Re: [PATCH edk2-platforms 1/7] Platform
> -Original Message-
> From: Leif Lindholm
> Sent: Thursday, June 18, 2020 3:38 PM
> To: Wasim Khan (OSS)
> Cc: devel@edk2.groups.io; Meenakshi Aggarwal
> ; Varun Sethi ;
> ard.biesheu...@arm.com; Wasim Khan
> Subject: Re: [PATCH edk2-platforms 2/7] Silicon/N
> -Original Message-
> From: Leif Lindholm
> Sent: Wednesday, June 17, 2020 8:24 PM
> To: Wasim Khan (OSS)
> Cc: devel@edk2.groups.io; Meenakshi Aggarwal
> ; Varun Sethi ;
> ard.biesheu...@arm.com; Wasim Khan
> Subject: Re: [PATCH edk2-platforms 2/8] Silicon/N
From: Wasim Khan
NXP SoCs supports different Serdes protocols using reset
configuration word (RCW).
Based on Serdes protocol value in reset configuration word (RCW)
different IP blocks gets enabled in HW.
This patch add Serdes support for LX2160A, which has 3 Serdes.
Changes in V2
From: Wasim Khan
Update DEBUG log to indicate SerDes protocol
is in hex.
Signed-off-by: Wasim Khan
---
Changes in V2:
- New Commit
Silicon/NXP/Library/SerDesHelperLib/SerDesHelperLib.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Silicon/NXP/Library/SerDesHelperLib
From: Wasim Khan
Based on SerDes protocol value in reset configuration word (RCW)
different IP blocks gets enabled in HW.
Add SoC specific SerDes configuration for LX2160A, which can be
used by different IPs to know the enabled interfaces and perform
the required initialization.
Signed-off-by
From: Wasim Khan
Change SerDes1ConfigTable type to STATIC and add module
prefix.
Signed-off-by: Wasim Khan
---
Changes in V2:
- New Commit
Silicon/NXP/LS1043A/Library/SocLib/SerDes.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Silicon/NXP/LS1043A/Library/SocLib
> -Original Message-
> From: Leif Lindholm
> Sent: Tuesday, June 16, 2020 8:50 PM
> To: Wasim Khan (OSS)
> Cc: devel@edk2.groups.io; Meenakshi Aggarwal
> ; Varun Sethi ;
> ard.biesheu...@arm.com; Wasim Khan
> Subject: Re: [PATCH edk2-platforms 1/1] Silicon/
From: Wasim Khan
Add SocGetSvr API to get the System Version Register(SVR)
Signed-off-by: Wasim Khan
---
Silicon/NXP/LX2160A/Library/SocLib/SocLib.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/Silicon/NXP/LX2160A/Library/SocLib/SocLib.c
b/Silicon/NXP/LX2160A/Library
From: Wasim Khan
Enable generic PCIe drivers and Wire up PciHostBridgeLib,
PciSegmentLib and PciCpuIo2Dxe.
Signed-off-by: Wasim Khan
---
Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc | 9 +
Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf | 7 +++
2 files changed, 16 insertions
From: Wasim Khan
Define macros to retrieve System Version Register(SVR)
related information
Signed-off-by: Wasim Khan
---
Silicon/NXP/Chassis2/Include/Chassis.h | 4
1 file changed, 4 insertions(+)
diff --git a/Silicon/NXP/Chassis2/Include/Chassis.h
b/Silicon/NXP/Chassis2/Include
From: Wasim Khan
System Version Register(SVR) is used to provide the SoC details
like Manufacturer ID, SoC Family, SoC major and minor version
etc.
DEVDISRn is used to disable unused peripherals.
Update Device Configuration structure for SVR and DEVDISRn.
Signed-off-by: Wasim Khan
From: Wasim Khan
Define System Version Register(SVR) for LS1043A SoC
Signed-off-by: Wasim Khan
---
Silicon/NXP/LS1043A/Include/Soc.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Silicon/NXP/LS1043A/Include/Soc.h
b/Silicon/NXP/LS1043A/Include/Soc.h
index 97a77d3f5da6..21b0dafffe91
From: Wasim Khan
Define System Version Register(SVR) for LX2160A SoC
Signed-off-by: Wasim Khan
---
Silicon/NXP/LX2160A/Include/Soc.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Silicon/NXP/LX2160A/Include/Soc.h
b/Silicon/NXP/LX2160A/Include/Soc.h
index 52674ee5f32c..6c745d580a6d
From: Wasim Khan
NXP SoCs supports different Serdes protocols using reset
configuration word (RCW).
Based on Serdes protocol value in reset configuration word (RCW)
different IP blocks gets enabled in HW.
This patch add Serdes support for LX2160A, which has 3 Serdes.
This patch has
From: Wasim Khan
System Version Register(SVR) is used to provide the SoC details
like Manufacturer ID, SoC Family, SoC major and minor version
etc.
DEVDISRn is used to disable unused peripherals.
This patch series update device configuration structure (DCFG)
for SVR and DEVDISRn for LS1043A
From: Wasim Khan
Add SocGetSvr API to get the System Version Register(SVR)
Signed-off-by: Wasim Khan
---
Silicon/NXP/Include/Library/SocLib.h| 7 +++
Silicon/NXP/LS1043A/Library/SocLib/SocLib.c | 14 ++
2 files changed, 21 insertions(+)
diff --git a/Silicon/NXP
From: Wasim Khan
Add PCIe space in VirtualMemoryMap
Signed-off-by: Wasim Khan
---
Silicon/NXP/LX2160A/Include/Soc.h | 8
+
Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c | 38
+++-
2 files changed, 45 insertions
From: Wasim Khan
Enable PlatformDxe driver for LX2160aRdbPkg
Signed-off-by: Wasim Khan
---
Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc | 2 ++
Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf | 3 +++
2 files changed, 5 insertions(+)
diff --git a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc
b
From: Wasim Khan
This patch series adds PCIe support for LX2160aRdbPkg.
LX2160-Rev1 and LX2160-Rev2 has different PCIe controller. Platform
driver checks the SoC version and enable corresponding PCIe controller
and its feature using dynamic PCDs.
PciHostBridgeLib and PciSegmentLib already has
From: Wasim Khan
System Version Register(SVR) is used to provide the SoC details
like Manufacturer ID, SoC Family, SoC major and minor version
etc.
DEVDISRn is used to disable unused peripherals.
Update Device Configuration structure for SVR and DEVDISRn.
Signed-off-by: Wasim Khan
From: Wasim Khan
Enable NetworkPkg for LX2160aRdbPkg Platform.
Signed-off-by: Wasim Khan
---
Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc | 11 +++
Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf | 5 +
2 files changed, 16 insertions(+)
diff --git a/Platform/NXP/LX2160aRdbPkg
From: Wasim Khan
Add PlatformDxe to do platform specific work.
At present it perform platform specific Pci initialization.
Signed-off-by: Wasim Khan
---
Platform/NXP/LX2160aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf | 35 +
Platform/NXP/LX2160aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
From: Wasim Khan
Based on SerDes protocol value in reset configuration word (RCW)
different IP blocks gets enabled in HW.
Add SoC specific SerDes configuration for LX2160A, which can be
used by different IPs to know the enabled interfaces and perform
the required initialization.
Signed-off-by
From: Wasim Khan
PCIe Layerscape controller in LX2160A-Rev2 is not completely
ECAM-compliant. It is non-ECAM only for the root bus (bus 0)
and for any other bus underneath the root bus it does support
ECAM access.
One approach can be to setup the controller in firmware and
expose bus[0x1-0xff
From: Wasim Khan
Define PCIe related PCDs for LX2160A.
Signed-off-by: Wasim Khan
---
Silicon/NXP/LX2160A/LX2160A.dsc.inc | 5 +
1 file changed, 5 insertions(+)
diff --git a/Silicon/NXP/LX2160A/LX2160A.dsc.inc
b/Silicon/NXP/LX2160A/LX2160A.dsc.inc
index fe8ed402fc4e..43e361464c8e 100644
From: Wasim Khan
Define macros to retrieve System Version Register(SVR)
related information
Signed-off-by: Wasim Khan
---
Silicon/NXP/Chassis3V2/Include/Chassis.h | 4
1 file changed, 4 insertions(+)
diff --git a/Silicon/NXP/Chassis3V2/Include/Chassis.h
b/Silicon/NXP/Chassis3V2/Include
From: Wasim Khan
Based on the serdes protocol value in reset configuration
word (RCW), different PCIe controllers are enabled.
Get SerDes protocol map and initialize only enabled PCIe
controllers.
Signed-off-by: Wasim Khan
Reviewed-by: Leif Lindholm
---
Notes:
Changes in V5:
- No
From: Wasim Khan
Implement SerDesHelperLib to provide helper functions which
can be used for SoC specific SerDes configuration.
Signed-off-by: Wasim Khan
---
Notes:
Changes in V4:
- No Change
Changes in V3:
- Change variable name LanePrtc to LaneProtocol
Changes in V2
From: Wasim Khan
NXP SoCs supports different Serdes protocols using reset
configuration word (RCW).
Based on Serdes protocol value in reset configuration word (RCW)
different IP blocks gets enabled in HW.
This patch series implements SerDesHelperLib and provide SoC specific
serdes
From: Wasim Khan
NXP SoCs supports different Serdes protocols using reset
configuration word (RCW).
Based on Serdes protocol value in reset configuration word (RCW)
different IP blocks gets enabled in HW.
This patch series implements SerDesHelperLib and provide SoC specific
serdes
From: Wasim Khan
Based on the serdes protocol value in reset configuration
word (RCW), different PCIe controllers are enabled.
Get SerDes protocol map and initialize only enabled PCIe
controllers.
Signed-off-by: Wasim Khan
Reviewed-by: Leif Lindholm
---
Notes:
Changes in V4:
- No
From: Wasim Khan
Implement SerDesHelperLib to provide helper functions which
can be used for SoC specific SerDes configuration.
Signed-off-by: Wasim Khan
---
Notes:
Changes in V5:
- No Change
Changes in V4:
- No Change
Changes in V3:
- Change variable name LanePrtc
From: Wasim Khan
Based on SerDes protocol value in reset configuration word (RCW)
different IP blocks gets enabled in HW.
Add SoC specific SerDes configuration for LS1043A, which can be
used by different IPs to know the enabled interfaces and perform
the required initialization.
Signed-off-by
From: Wasim Khan
Based on SerDes protocol value in reset configuration word (RCW)
different IP blocks gets enabled in HW.
Add SoC specific SerDes configuration for LS1043A, which can be
used by different IPs to know the enabled interfaces and perform
the required initialization.
Signed-off-by
From: Wasim Khan
Based on the serdes protocol value in reset configuration
word (RCW), different PCIe controllers are enabled.
Get SerDes protocol map and initialize only enabled PCIe
controllers.
Signed-off-by: Wasim Khan
Reviewed-by: Leif Lindholm
---
Notes:
Changes in V3:
- No
From: Wasim Khan
Based on SerDes protocol value in reset configuration word (RCW)
different IP blocks gets enabled in HW.
Add SoC specific SerDes configuration for LS1043A, which can be
used by different IPs to know the enabled interfaces and perform
the required initialization.
Signed-off-by
From: Wasim Khan
NXP SoCs supports different Serdes protocols using reset
configuration word (RCW).
Based on Serdes protocol value in reset configuration word (RCW)
different IP blocks gets enabled in HW.
This patch series implements SerDesHelperLib and provide SoC specific
serdes
From: Wasim Khan
Implement SerDesHelperLib to provide helper functions which
can be used for SoC specific SerDes configuration.
Signed-off-by: Wasim Khan
---
Notes:
Changes in V3:
- Change variable name LanePrtc to LaneProtocol
Changes in V2:
- Addressed review comments for
> -Original Message-
> From: Leif Lindholm
> Sent: Monday, June 8, 2020 9:00 PM
> To: Wasim Khan (OSS)
> Cc: devel@edk2.groups.io; Meenakshi Aggarwal
> ; Varun Sethi ;
> ard.biesheu...@arm.com; Wasim Khan
> Subject: Re: [PATCH edk2-platforms v2 2/3] Silicon/
From: Wasim Khan
NXP SoCs supports different Serdes protocols using reset
configuration word (RCW).
Based on Serdes protocol value in reset configuration word (RCW)
different IP blocks gets enabled in HW.
This patch series implements SerDesHelperLib and provide SoC specific
serdes
From: Wasim Khan
Based on the serdes protocol value in reset configuration
word (RCW), different PCIe controllers are enabled.
Get SerDes protocol map and initialize only enabled PCIe
controllers.
Signed-off-by: Wasim Khan
---
Notes:
Changes in V2:
- Addressed review comments for
From: Wasim Khan
Based on SerDes protocol value in reset configuration word (RCW)
different IP blocks gets enabled in HW.
Add SoC specific SerDes configuration for LS1043A, which can be
used by different IPs to know the enabled interfaces and perform
the required initialization.
Signed-off-by
From: Wasim Khan
Implement SerDesHelperLib to provide helper functions which
can be used for SoC specific SerDes configuration.
Signed-off-by: Wasim Khan
---
Notes:
Changes in V2:
- Addressed review comments for structure, variable and function names
- Using BIT0 instead of 0x1u
> -Original Message-
> From: Leif Lindholm
> Sent: Friday, June 5, 2020 6:06 PM
> To: Wasim Khan (OSS)
> Cc: devel@edk2.groups.io; Meenakshi Aggarwal
> ; Varun Sethi ;
> ard.biesheu...@arm.com; Wasim Khan
> Subject: Re: [PATCH edk2-platforms 2/3] Silicon/
From: Wasim Khan
Based on the serdes protocol value in reset configuration
word (RCW), different PCIe controllers are enabled.
Get serdes protocol map and initialize only enabled PCIe
controllers.
Signed-off-by: Wasim Khan
---
Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf | 1
From: Wasim Khan
Implement SerDesHelperLib to provide helper functions which
can be used for SoC specific serdes configuration.
Signed-off-by: Wasim Khan
---
Silicon/NXP/NxpQoriqLs.dec | 1 +
Silicon/NXP/Library/SerDesHelperLib/SerDesHelperLib.inf | 28
From: Wasim Khan
NXP SoCs supports different serdes protocols using reset
configuration word (RCW).
Based on serdes protocol value in reset configuration word (RCW)
different IP blocks gets enabled in HW.
This patch series implements SerDesHelperLib and provide SoC specific
serdes
From: Wasim Khan
Based on serdes protocol value in reset configuration word (RCW)
different IP blocks gets enabled in HW.
Add SoC specific serdes configuration for LS1043A, which can be
used by different IPs to know the enabled interfaces and perform
the required initialization.
Signed-off-by
> -Original Message-
> From: Philippe Mathieu-Daudé
> Sent: Monday, June 1, 2020 2:17 PM
> To: devel@edk2.groups.io; Wasim Khan
> Cc: michael.d.kin...@intel.com; liming@intel.com; Varun Sethi
>
> Subject: Re: [edk2-devel] [PATCH v2] MdePkg: Include Acpi hea
From: Wasim Khan
Add PCIe related PCDs.
Co-authored-by: Vabhav Sharma
Co-authored-by: Wasim Khan
Signed-off-by: Wasim Khan
---
Notes:
V2:
- Removed Signed-off and added Co-authored-by for co-author
- Droped PcdPciDebug
Silicon/NXP/NxpQoriqLs.dec | 8
1 file changed, 8
From: Wasim Khan
PCIe Layerscape Gen4 controller is not ECAM compliant and have
different PCI config space region for bus 0 (Controller space) and
bus[0x1-0xff] on NXP SoCs.
For config transactions for Bus0:
- Config transaction address = PCIe controller address + offset
For config
From: Wasim Khan
With PCIe LsGen4 controller, clearing the Bus Master Enable bit in
Command register blocks all outbound transactions to be sent out
in RC mode.
According to PCI Express base specification, the Command register’s
Bus Master Enable bit of a PCI Express RC controller can only
From: Wasim Khan
Increase fv image size to pass debug build.
Signed-off-by: Wasim Khan
Acked-by: Ard Biesheuvel
---
Notes:
V2:
- No change
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/Platform/NXP
From: Wasim Khan
Dump ATU windows for PCIe LsGen4 controller.
Co-authored-by: Vabhav Sharma
Co-authored-by: Wasim Khan
Signed-off-by: Wasim Khan
---
Notes:
V2:
- Removed Signed-off and added Co-authored-by for co-author
- Drop PcdPciDebug and use DEBUG_CODE_BEGIN/DEBUG_CODE_END
From: Wasim Khan
When PCIe Layerscape Gen4 controller is sending multiple split
completions and ACK latency expires indicating that ACK should
be send at priority. But because of large number of split completions
and FC update DLLP,the controller does not give priority to ACK
transmission. This
From: Wasim Khan
Implement PciHostBridgeLib that exposes the PCIe root complexes to
the generic PCI host bridge driver.
Setup PCIe Layerscape Controller and setup CFG, IO,
MMIO and MMIO64 iATU windows.
Co-authored-by: Vabhav Sharma
Co-authored-by: Wasim Khan
Signed-off-by: Wasim Khan
From: Wasim Khan
Add PCIe Support for NXP Layerscape SoC which supports
different PCIe controllers.
Use generic PCIe drivers and wire up PciHostBridgeLib,
PciSegmentLib and PciCpuIo2Dxe driver for controller
specific implementation.
V1 Series can be referred here:
https://edk2.groups.io/g/devel
From: Wasim Khan
Define PCIe related PCDs for LS1043A.
Co-authored-by: Vabhav Sharma
Co-authored-by: Wasim Khan
Signed-off-by: Wasim Khan
---
Notes:
V2:
- Removed Signed-off and added Co-authored-by for co-author
- Dropped PcdPciDebug
Silicon/NXP/LS1043A/LS1043A.dsc.inc | 7
From: Wasim Khan
We have different PCI config space region for bus 0 (Controller space) and
bus[0x1-0xff] on NXP SoCs with PCIe LS controller.
Add PciSegmentLib for PCIe LS controller.
For config transactions for Bus0:
- Config transaction address = PCIe controller address + offset
For
From: Wasim Khan
Setup PCIe LayerscapeGen4 controller and setup CFG, IO,
MMIO and MMIO64 iATU windows.
Check for PcdPciLsGen4Ctrl to enable LsGen4 PCIe
controller.
Co-authored-by: Vabhav Sharma
Co-authored-by: Wasim Khan
Signed-off-by: Wasim Khan
---
Notes:
V2:
- Removed Signed-off
From: Meenakshi Aggarwal
Enable NetworkPkg for LS1043aRdb Platform.
Signed-off-by: Wasim Khan
---
Notes:
V2:
- Change author
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 11 +++
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 5 +
2 files changed, 16 insertions
From: Wasim Khan
Dump ATU windows for PCIe Layerscape controller.
Signed-off-by: Wasim Khan
---
Notes:
V2:
- Drop PcdPciDebug and use DEBUG_CODE_BEGIN/DEBUG_CODE_END
- Passing Max window number as argument to LsDumpAtu()
Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
From: Wasim Khan
NXP SoC has multiple PCIe RCs and there is no fix translation
offset between I/O port accesses and MMIO accesses.
Add PciCpuIo2Dxe driver to implement EFI_CPU_IO2_PROTOCOL
to add the translation for different RCs for IO access.
Signed-off-by: Wasim Khan
Reviewed-by: Ard
From: Wasim Khan
PCIe Layerscape controller can be enabled for ECAM style
configuration access using CFG SHIFT Feature.
Check for PcdPciCfgShiftEnable to decide the configuration access
scheme to be used with PCIe LS controller.
Signed-off-by: Wasim Khan
---
Notes:
V2:
- Addressed
From: Wasim Khan
PCIe layerscape controller supports CFG Shift feature. It can be
enabled by setting BIT[28] of iATU Control 2 Register.
Check PcdPciCfgShiftEnable to enable 'CFG Shift feature' in
PCIe controller.
if enable, PCIe layerscape controller shifts BDF from bits[27:12] to
From: Wasim Khan
Enable generic PCIe drivers and Wire up PciHostBridgeLib,
PciSegmentLib and PciCpuIo2Dxe.
Signed-off-by: Wasim Khan
---
Notes:
V2:
- No change
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 9 +
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 7 +++
2
> -Original Message-
> From: Jon Nettleton
> Sent: Monday, May 25, 2020 10:00 AM
> To: Wasim Khan (OSS)
> Cc: Ard Biesheuvel ; devel@edk2.groups.io;
> Meenakshi Aggarwal ; Vabhav Sharma
> ; Varun Sethi ;
> l...@nuviainc.com
> Subject: Re: [PATCH edk2-p
> -Original Message-
> From: Ard Biesheuvel
> Sent: Friday, May 22, 2020 3:00 PM
> To: Wasim Khan (OSS) ; devel@edk2.groups.io;
> Meenakshi Aggarwal ; Vabhav Sharma
> ; Varun Sethi ;
> l...@nuviainc.com; j...@solid-run.com
> Cc: Wasim Khan
> Subject: Re:
> -Original Message-
> From: Ard Biesheuvel
> Sent: Friday, May 22, 2020 3:08 PM
> To: Wasim Khan (OSS) ; devel@edk2.groups.io;
> Meenakshi Aggarwal ; Vabhav Sharma
> ; Varun Sethi ;
> l...@nuviainc.com; j...@solid-run.com
> Cc: Wasim Khan
> Subject: Re:
> -Original Message-
> From: Ard Biesheuvel
> Sent: Friday, May 22, 2020 2:42 PM
> To: Wasim Khan (OSS) ; devel@edk2.groups.io;
> Meenakshi Aggarwal ; Vabhav Sharma
> ; Varun Sethi ;
> l...@nuviainc.com; j...@solid-run.com
> Cc: Wasim Khan
> Subject: Re:
> -Original Message-
> From: Leif Lindholm
> Sent: Friday, May 22, 2020 4:29 PM
> To: Ard Biesheuvel
> Cc: Wasim Khan (OSS) ; devel@edk2.groups.io;
> Meenakshi Aggarwal ; Vabhav Sharma
> ; Varun Sethi ; jon@solid-
> run.com; Wasim Khan
> Subject: Re: [PATC
> -Original Message-
> From: Ard Biesheuvel
> Sent: Friday, May 22, 2020 3:10 PM
> To: Wasim Khan (OSS) ; devel@edk2.groups.io;
> Meenakshi Aggarwal ; Vabhav Sharma
> ; Varun Sethi ;
> l...@nuviainc.com; j...@solid-run.com
> Cc: Wasim Khan
> Subject: Re:
> -Original Message-
> From: Ard Biesheuvel
> Sent: Friday, May 22, 2020 2:55 PM
> To: Wasim Khan (OSS) ; devel@edk2.groups.io;
> Meenakshi Aggarwal ; Vabhav Sharma
> ; Varun Sethi ;
> l...@nuviainc.com; j...@solid-run.com
> Cc: Wasim Khan
> Subject: Re:
> -Original Message-
> From: Ard Biesheuvel
> Sent: Friday, May 22, 2020 3:06 PM
> To: Wasim Khan (OSS) ; devel@edk2.groups.io;
> Meenakshi Aggarwal ; Vabhav Sharma
> ; Varun Sethi ;
> l...@nuviainc.com; j...@solid-run.com
> Cc: Wasim Khan
> Subject: Re:
From: Wasim Khan
NXP SoC has multiple PCIe RCs and there is no fix translation
offset between I/O port accesses and MMIO accesses.
Add PciCpuIo2Dxe driver to implement EFI_CPU_IO2_PROTOCOL
to add the translation for different RCs for IO access.
Signed-off-by: Wasim Khan
---
Silicon/NXP
From: Wasim Khan
Define PCIe related PCDs for LS1043A.
Signed-off-by: Vabhav Sharma
Signed-off-by: Wasim Khan
---
Silicon/NXP/LS1043A/LS1043A.dsc.inc | 8
1 file changed, 8 insertions(+)
diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
index
From: Wasim Khan
Dump ATU windows for PCIe LsGen4 controller if PcdPciDebug
is enabled.
Signed-off-by: Vabhav Sharma
Signed-off-by: Wasim Khan
---
.../Library/PciHostBridgeLib/PciHostBridgeLib.inf | 1 +
.../Library/PciHostBridgeLib/PciHostBridgeLib.c| 34 ++
2
From: Wasim Khan
Add PCIe related PCDs.
Signed-off-by: Vabhav Sharma
Signed-off-by: Wasim Khan
---
Silicon/NXP/NxpQoriqLs.dec | 9 +
1 file changed, 9 insertions(+)
diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index 0722f59ef4f6..bafdfd9f4298 100644
--- a
From: Wasim Khan
Add PCIe Support for NXP Layerscape SoC which supports
different PCIe controllers.
Use generic PCIe drivers and wire up PciHostBridgeLib,
PciSegmentLib and PciCpuIo2Dxe driver for controller
specific implementation.
Wasim Khan (16):
Silicon/NXP/NxpQoriqLs.dec: Add PCIe
From: Wasim Khan
PCIe Layerscape Gen4 controller is not ECAM complaint and have
different PCI config space region for bus 0 (Controller space) and
bus[0x1-0xff] on NXP SoCs.
For config transactions for Bus0:
- Config transaction address = PCIe controller address + offset
For config
From: Wasim Khan
PCIe Layerscape controller can be enabled for ECAM style
configuration access using CFG SHIFT Feature.
Check for PcdPciCfgShiftEnable to decide the configuration access
scheme to be used with PCIe LS controller.
Signed-off-by: Wasim Khan
---
Silicon/NXP/Library/PciSegmentLib
From: Wasim Khan
Setup PCIe LayerscapeGen4 controller and setup CFG, IO,
MMIO and MMIO64 iATU windows.
Check for PcdPciLsGen4Ctrl to enable LsGen4 PCIe
controller.
Signed-off-by: Vabhav Sharma
Signed-off-by: Wasim Khan
---
Silicon/NXP/NxpQoriqLs.dec | 1
From: Wasim Khan
When PCIe Layerscape Gen4 controller is sending multiple split
completions and ACK latency expires indicating that ACK should
be send at priority. But because of large number of split completions
and FC update DLLP,the controller does not give priority to ACK
transmission. This
From: Wasim Khan
With PCIe LsGen4 controller, clearing the Bus Master Enable bit in
Command register blocks all outbound transactions to be sent out
in RC mode.
According to PCI Express base specification, the Command register’s
Bus Master Enable bit of a PCI Express RC controller can only
From: Wasim Khan
Enable generic PCIe drivers and Wire up PciHostBridgeLib,
PciSegmentLib and PciCpuIo2Dxe.
Signed-off-by: Wasim Khan
---
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 9 +
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 7 +++
2 files changed, 16 insertions
From: Wasim Khan
We have different PCI config space region for bus 0 (Controller space) and
bus[0x1-0xff] on NXP SoCs with PCIe LS controller.
Add PciSegmentLib for PCIe LS controller.
For config transactions for Bus0:
- Config transaction address = PCIe controller address + offset
For
From: Wasim Khan
PCIe layerscape controller supports CFG Shift feature. It can be
enabled by setting BIT[28] of iATU Control 2 Register.
Check PcdPciCfgShiftEnable to enable 'CFG Shift feature' in
PCIe controller.
if enable, PCIe layerscape controller shifts BDF from bits[27:12] to
From: Wasim Khan
Implement PciHostBridgeLib that exposes the PCIe root complexes to
the generic PCI host bridge driver.
Setup PCIe Layerscape Controller and setup CFG, IO,
MMIO and MMIO64 iATU windows.
Signed-off-by: Vabhav Sharma
Signed-off-by: Wasim Khan
---
.../Library/PciHostBridgeLib
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